z8fmc16100 ZiLOG Semiconductor, z8fmc16100 Datasheet - Page 190

• Manufacturer Part Number: z8fmc16100
• Description: Z8 Encore Motor Control Flash Mcus
• Manufacturer: ZiLOG Semiconductor

s
PS024611-0408
S
Slave Address
Figure 33. Data Transfer Format—Slave Receive Transaction with 10-Bit Address
1st Byte
8. The master sends the
Slave Receive Transaction with 10-Bit Address
The data transfer format for writing data from a master to a slave with 10-bit addressing is
shown in
operating as a slave in 10-bit addressing mode and receiving data from the bus master.
1. The software configures the controller for operation as a slave in 10-bit addressing
2. The master initiates a transfer, sending the first address byte. The I
3. The master sends the second address byte. The SLAVE mode I
4. The software responds to the interrupt by reading the I2CISTAT register, which clears
5. The master detects the Acknowledge and sends the first byte of data.
cause the I
register). Because the slave received data from the master, the software takes no action
in response to the STOP interrupt other than reading the I2CISTAT register to clear the
STOP
mode, as follows:
(a) Initialize the
(b) Optionally set the
(c) Initialize the
(d) Set
nizes the start of a 10-bit address with a match to
0 (a Write from the master to the slave). The I
it is available to accept the transaction.
address match between the second address byte and
I2CISTAT register is set to 1, thereby causing an interrupt. The
indicating a Write to the slave. The I
able to accept the data.
the
first byte of data is received. If the software is only able to accept a single byte, it sets
the
SAM
NAK
or MASTER/SLAVE mode with 10-bit addressing.
the I2CMODE register.
Figure
W=0
bit in the I2CISTAT register.
IEN
bit. Because
bit in the I2CCTL register.
2
C controller to assert a STOP interrupt (the
33. The procedure that follows describes the I
= 1 in the I2CCTL register. Set
A
MODE
SLA[7:0]
Slave Address
RD
STOP
GCE
field in the I2CMODE register for either SLAVE ONLY mode
2nd Byte
= 0, no immediate action is taken by the software until the
bit.
or
bits in the I2CSLVAD register and the
RESTART
2
C controller acknowledges, indicating it is avail-
A
signal on the bus. Either of these signals can
NAK
Data
2
C controller acknowledges, indicating
SLA[9:8]
= 0 in the I
SLA[7:0]
A
STOP
2
C Master/Slave Controller
2
Product Specification
and detects the R/W bit =
C Control register.
bit = 1 in the I2CISTAT
Data
2
C controller detects an
. The
RD
2
bit is cleared to 0,
C controller recog-
SLA[9:8]
Slave Transactions
SAM
A/A
bit in the
P/S
bits in
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