z8fmc16100 ZiLOG Semiconductor, z8fmc16100 Datasheet - Page 65

• Manufacturer Part Number: z8fmc16100
• Description: Z8 Encore Motor Control Flash Mcus
• Manufacturer: ZiLOG Semiconductor

Table 30. Interrupt Request 0 Register (IRQ0)
BITS
FIELD
RESET
R/W
ADDR
PS024611-0408
Interrupt Control Register Definitions
Software Interrupt Assertion
Interrupt Request 0 Register
PWMI
R/W
7
0
Program code can generate interrupts directly. Writing a 1 to the appropriate bit in the
Interrupt Request register triggers an interrupt (assuming that interrupt is enabled). This
bit is automatically cleared when the eZ8 CPU vectors to the ISR.
The following style of coding to generate software interrupts by setting bits in the
Interrupt Request registers is not recommended. All incoming interrupts that are received
between execution of the first LDX command and the last LDX command are lost.
The following code segment is an example of a poor coding style that results in lost
interrupt requests:
To avoid missing interrupts, Zilog
in the Interrupt Request registers:
The interrupt control registers enable individual interrupts, set interrupt priorities, and
indicate interrupt requests.
The Interrupt Request 0 (IRQ0) register
vectored and polled interrupts. When a request is presented to the interrupt controller, the
corresponding bit in the IRQ0 register becomes 1. If interrupts are globally enabled
(vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU reads the Interrupt
Request 0 register to determine if any interrupt requests are pending.
LDX r0, IRQ0
OR r0, MASK
LDX IRQ0, r0
ORX IRQ0, MASK
FLTI
R/W
6
0
ADCI
R/W
5
0
CMPI
R/W
®
4
0
recommends the following style of coding to set bits
FC0H
(Table
R/W
T0I
3
0
30) stores the interrupt requests for both
Z8FMC16100 Series Flash MCU
U0RXI
R/W
2
0
Product Specification
Software Interrupt Assertion
U0TXI
R/W
1
0
R/W
SPII
0
0
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