z8fmc16100 ZiLOG Semiconductor, z8fmc16100 Datasheet - Page 182

• Manufacturer Part Number: z8fmc16100
• Description: Z8 Encore Motor Control Flash Mcus
• Manufacturer: ZiLOG Semiconductor

PS024611-0408
S
Note:
Slave Address
Figure 29. Data Transfer Format—Master Write Transaction with a 10-Bit Address
1st Byte
11. The I
12. The I
13. The I
14. If more bytes remain to be sent, return to Step 9.
15. When there is no more data to be sent, the software responds by setting the
16. If no additional transaction is queued by the master, the software can clear the
17. The I
18. The I
If the slave terminates the transaction early by responding with a Not Acknowledge during
the transfer, the I
terminate the transaction by setting either the
(end this transaction, start a new one). In this case, it is not necessary for software to set
the
transmitted. The I
acknowledge case.
Master Write Transaction with a 10-Bit Address
Figure 29
The first seven bits transmitted in the first byte are
most significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
FLUSH
High period of SCL. The I
If the slave does not acknowledge the address byte, the I
bit in the I
register. The software responds to the Not Acknowledge interrupt by setting the
bit and clearing the
sends a
is complete, and the following steps can be ignored.
I
transmit interrupt asserts.
the I
of the I
2
C Data register.
2
2
2
2
2
2
C Control register (or the
displays the data transfer format from a master to a 10-bit addressed slave.
C slave sends an Acknowledge (by pulling the SDA signal Low) during the next
C controller loads the contents of the I
C controller shifts the data out via the SDA signal. After the first bit is sent, the
C controller completes transmission of the data on the SDA signal.
C controller sends a
bit of the I2CCTL register to flush the data that was previously written but not
2
W=0
STOP
C Control register.
2
C Status register, sets the
2
condition on the bus, and clears the
2
C controller asserts the
C controller hardware automatically flushes transmit data in this not
A
TXI
Slave Address
2nd Byte
bit. The I
2
STOP
C controller sets the ACK bit in the I
START
condition to the I
2
C controller flushes the Transmit Data register,
ACKV
NCKI
bit to initiate a new transaction).
A
STOP
bit, and clears the
interrupt and halts. The software must
2
Data
C Shift register with the contents of the
11110XX
bit (end transaction) or the
STOP
2
C bus.
A
and
2
. The two
C controller sets the NCKI
NCKI
Product Specification
Data
ACK
2
C Status register.
bits. The transaction
bit in the I
XX
Master Transactions
bits are the two
A/A
STOP
START
2
C State
TXI
STOP
bit of
F/S
bit
bit
170