z8fmc16100 ZiLOG Semiconductor, z8fmc16100 Datasheet - Page 166

• Manufacturer Part Number: z8fmc16100
• Description: Z8 Encore Motor Control Flash Mcus
• Manufacturer: ZiLOG Semiconductor

PS024611-0408
SPI Interrupts
SPI Baud Rate Generator
The next time SS asserts, the MISO pin outputs SPIDAT[7], regardless of where the
previous transaction suspended. Writing a 1 to
When SPI interrupts are enabled, the SPI generates an interrupt after character
transmission/reception is completed in both MASTER and SLAVE modes. A character
can be defined to be 1–8 bits by the NUMBITS field in the SPI Mode register. In SLAVE
mode, it is not necessary for SS to deassert between characters to generate an interrupt.
The SPI in SLAVE mode can also generate an interrupt if the SS signal deasserts prior to
transfer of all the bits in a character (see description of slave abort error above). Writing a
1 to the IRQ bit in the SPI Status register clears the pending SPI interrupt request. The
IRQ
To start the transfer process, an SPI interrupt can be forced by software to write a 1 to the
STR bit in the SPICTL register.
If the SPI is disabled, an SPI interrupt can be generated by a Baud Rate Generator timeout.
This timer function must be enabled by setting the
Baud Rate Generator timeout does not set the
interrupt bit in the interrupt controller.
In SPI MASTER mode, the Baud Rate Generator creates a lower-frequency serial clock
(SCK) for data transmission synchronization between the master and the external slave.
The input to the Baud Rate Generator is from the system clock. The SPI Baud Rate High
and Low Byte registers combine to form a 16-bit reload value, BRG[15:0], for the SPI
Baud Rate Generator. The SPI baud rate is calculated using the following equation:
Minimum baud rate is obtained by setting BRG[15:0] to
of (2 x 65536 = 131072).
When the SPI is disabled, the Baud Rate Generator can function as a basic 16-bit timer
with an interrupt upon timeout. To configure the Baud Rate Generator as a timer with an
interrupt upon timeout, complete the following procedure:
1. Disable the SPI by clearing the SPIEN bit in the SPI Control register to 0.
2. Load the appropriate 16-bit count value into the SPI Baud Rate High and Low Byte
3. Enable the Baud Rate Generator timer function and the associated interrupt by setting
SPI Baud Rate (bps) =
registers.
the
bit must be cleared to 0 by the interrupt service routine to generate future interrupts.
BIRQ
bit in the SPI Control register to 1.
System Clock Frequency (Hz)
2 x BRG[15:0]
IRQ
ABT
bit in the SPISTAT register, just the SPI
clears this error flag.
BIRQ
Z8FMC16100 Series Flash MCU
0000h
bit in the SPICTL register. This
Product Specification
for a clock divisor value
SPI Interrupts
154