z8fmc16100 ZiLOG Semiconductor, z8fmc16100 Datasheet - Page 192

• Manufacturer Part Number: z8fmc16100
• Description: Z8 Encore Motor Control Flash Mcus
• Manufacturer: ZiLOG Semiconductor

PS024611-0408
S Slave Address
1st Byte
Figure 35. Data Transfer Format—Slave Transmit Transaction with 10-Bit Address
4. SCL is released and the first data byte is shifted out.
5. After the first bit of the first data byte has been transferred, the I
6. The software responds to the transmit data interrupt (
7. After the data byte has been received by the master, the master transmits an
8. The bus cycles through steps 5 to 7 until the final byte has been transferred. If the
9. The software responds to the Not Acknowledge interrupt by clearing the
10. When the master has completed the final acknowledge cycle, it asserts a
11. The slave I
12. The software responds to the
Slave Transmit Transaction with 10-Bit Address
The data transfer format for a master reading data from a slave with 10-bit addressing is
shown in
operating as a slave in 10-bit addressing mode, transmitting data to the bus master.
W = 0 A Slave Address
to enable transmit interrupts. When the master initiates the data transfer, the I
controller holds SCL Low until the software has written the first data byte to the
I2CDATA register.
TDRE
data byte into the I2CDATA register, which clears
Acknowledge instruction (or Not Acknowledge instruction if this byte is the final data
byte).
software has not yet loaded the next data byte when the master brings SCL Low to
transfer the most significant data bit, the slave I
data register has been written. When a Not Acknowledge instruction is received by the
slave, the I
Acknowledge interrupt to be generated.
I2CCTL register and by asserting the
data register.
RESTART
I2CISTAT register).
register, which clears the
Figure
bit, which asserts the transmit data interrupt.
condition on the bus.
2
2
C controller sets the
C controller asserts the
2nd Byte
35. The following procedure describes the I
SPRS
A
STOP/RESTART
S Slave Address
bit.
NCKI
STOP/RESTART
FLUSH
1st Byte
bit in the I2CISTAT register, causing the Not
bit of the I2CCTL register to empty the
interrupt by reading the I2CISTAT
2
C controller holds SCL Low until the
TDRE
R = 1 A Data A Data A
interrupt (set
TDRE
.
2
C Master/Slave Controller
= 1) by loading the next
Product Specification
2
C controller sets the
SPRS
Slave Transactions
TXI
bit in
STOP
bit in the
2
C
or
P
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