z8fmc16100 ZiLOG Semiconductor, z8fmc16100 Datasheet - Page 255

• Manufacturer Part Number: z8fmc16100
• Description: Z8 Encore Motor Control Flash Mcus
• Manufacturer: ZiLOG Semiconductor

PS024611-0408
Automatic Reset
Break Points
The host transmits a Serial Break on the DBG pin when first connecting to the
Z8FMC16100 Series Flash MCU device or when recovering from an error. A Serial Break
from the host resets the Auto-Baud Generator/Detector but does not reset the OCD
Control register. A Serial Break leaves the device in DEBUG mode if that is the current
mode. The OCD is held in Reset until the end of the Serial Break when the DBG pin
returns High. Due to the open-drain nature of the DBG pin, the host can send a Serial
Break to the OCD even if the OCD is transmitting a character.
The Z8FMC16100 Series Flash MCU devices have the capability to switch clock sources
during operation. If the Auto-Baud is set and the clock source is switched, the Auto-Baud
value becomes invalid. A new Auto-Baud value must be configured with the new clock
frequency.
The oscillator control logic has clock switch detection. If a clock switch is detected and
the Auto-Baud is set, the device automatically sends a Serial Break for 4096 clocks. This
resets the Auto-Baud and indicate to the host that a new Auto-Baud character must be
sent.
Execution break points are generated using the BRK instruction (Opcode
eZ8 CPU decodes a BRK instruction, it signals the OCD. If break points are enabled, the
OCD idles the eZ8 CPU and enters DEBUG mode. If break points are not enabled, the
OCD ignores the BRK signal and the BRK instruction operates as a NOP instruction.
If break points are enabled, the OCD can be configured to automatically enter DEBUG
mode, or to loop on the break instruction. If the OCD is configured to loop on the BRK
instruction, then the CPU remains able to service DMA and interrupt requests.
The loop on BRK instruction can service interrupts in the background. For interrupts to be
serviced in the background, there cannot be any break points in the interrupt service
routine. Otherwise, the CPU stops on the break point in the interrupt routine. For
interrupts to be serviced in the background, interrupts must be enabled. Debugging soft-
ware does not automatically enable interrupts when using this feature. Interrupts are typi-
cally disabled during critical sections of code where interrupts do not occur (such as
adjusting the stack pointer or modifying shared data).
Host software can poll the IDLE bit of the OCDSTAT register to determine if the OCD is
looping on a BRK instruction. When software wants to stop the CPU on the BRK
instruction on which it is looping, software must not set the DBGMODE bit of the
OCDCTL register. The CPU may have vectored to an interrupt service routine. Instead,
software clears the BRKLP bit. This allows the CPU to finish the interrupt service routine it
may be in and return to the BRK instruction. When the CPU returns to the BRK instruction
Product Specification
00h
Automatic Reset
). When the
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