st20-gp1 STMicroelectronics, st20-gp1 Datasheet - Page 90

• Manufacturer Part Number: st20-gp1
• Description: Gps Processor
• Manufacturer: STMicroelectronics

ST20-GP1
15.4.1 Dreq/Dack protocol
In this mode the 2 control pins PlinknotReq (Dreq) and PlinknotAck (Dack) are active low. The
initial (inactive) state of the 2 control wires is high.
Dreq/Dack output
The sequence of events for a Dreq/Dack output is outlined below.
Dreq/Dack input
The sequence of events for a Dreq/Dack input is outlined below.
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1
2
3
1
2
3
4
PlinknotReq
(Dreq)
PlinknotAck
(Dack)
PlinkData0-7
PlinknotReq
(Dreq)
PlinknotAck
(Dack)
PlinkData0-7
The ST20-GP1 then asserts the PlinknotAck (Dack) output low.
The external ASIC applies the data to be transferred to the PlinkData0-7 pins. The ASIC
can then return PlinknotReq (Dreq) high at any time.
The data on the input pins is sampled, then PlinknotAck (Dack) is forced high.
PlinknotReq (Dreq), input to ST20, is taken low by the external ASIC.
The ST20-GP1 asserts the PlinknotAck (Dack) output low. The ASIC can then take
PlinknotReq (Dreq) high.
Following PlinknotAck (Dack) going low, the data in the DMA buffer is applied to the output
pins. PlinknotAck (Dack) is forced high and the output drivers are tristated. The ASIC can
initiate the next transfer.
PlinknotReq (Dreq), input to ST20, is taken low by the external ASIC.
Figure 15.1 Dreq/Dack protocol
ST20 Output
ST20 Input