st20-gp1 STMicroelectronics, st20-gp1 Datasheet - Page 82

• Manufacturer Part Number: st20-gp1
• Description: Gps Processor
• Manufacturer: STMicroelectronics

ST20-GP1
ASCIntEnable register
The ASCIntEnable register enables a source of interrupt.
Interrupts will occur when a status bit in the ASCStatus register is 1, and the corresponding bit in
the ASCIntEnable register is 1.
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ASCControl
Bit
2:0
4:3
5
6
7
8
15:9
Bit field
Mode
StopBits
ParityOdd
LoopBack
Run
RxEnable
ASC base address + #0C
Function
ASC mode control
Number of stop bits selection
Parity selection
Loopback mode enable bit
Baud rate generator run bit
Receiver enable bit
RESERVED. Write 0, will read back 0.
Mode2:0
000
001
010
011
100
101
110
111
StopBits1:0
00
01
10
11
0
1
0
1
0
1
0
1
Table 13.5 ASCControl register format
Even parity (parity bit set on odd number of ‘1’s in data)
Odd parity (parity bit set on even number of ‘1’s in data)
Standard transmit/receive mode
Loopback mode enabled
Baud rate generator disabled (ASC inactive)
Baud rate generator enabled
Receiver disabled
Receiver enabled
Number of stop bits
Mode
RESERVED
8-bit data
RESERVED
7-bit data + parity
9-bit data
8-bit data + wake up bit
RESERVED
8-bit data + parity
0.5 stop bits
1 stop bit
1.5 stop bits
2 stop bits
Read/Write