st20-gp1 STMicroelectronics, st20-gp1 Datasheet - Page 56

• Manufacturer Part Number: st20-gp1
• Description: Gps Processor
• Manufacturer: STMicroelectronics

ST20-GP1
in the following two cases:
The first case may be optimized slightly by making use of the DataDriveDelay configuration
register parameter, see Table 9.4. When this is used, the programmed BusReleaseTime may be
smaller, reducing the number of dead cycles, see Figure 9.4.
Note, if DataDriveDelay is used, it must be used for all banks. If this rule is not adhered to, bus
contention may occur on bank switches. For example, consider case 2 in Figure 9.4 above. If the
BusReleaseTime coincides with the dead cycle inserted due to a bank switch, contention will
occur unless DataDriveDelay is programmed in the same way as if no bank switch had occurred.
9.4
When enabled (see Table 9.4), MemWait is sampled at the midpoint of accesses which are
configured to be four cycles or greater. If the duration of the external access is not an even number
of cycles (i.e. the AccessDuration bit field in the EMIConfigData register, see Table 9.4, is an odd
number), MemWait is sampled on the internal rising clock edge just after the midpoint of the
access.
Once a high has been sampled, the access is stalled. MemWait suspends the state of the EMI in
the cycle after it is sampled high. The state remains suspended until MemWait is sampled low. Any
strobe edges scheduled to occur in the cycle after MemWait is sampled will not occur. Strobe
edges scheduled to occur on the same edge as MemWait is sampled are not affected. Figure 9.5
and Figure 9.6 show the extension of the external memory cycle and the delaying of strobe
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The previous access was a read and the pending one is a write. The write access will not
start until the programmed number of BusReleaseTime cycles have elapsed.
The previous access was to a different bank to the pending access (bank switch). One
cycle is always inserted between accesses to different banks. Note that, if the first condition
is also true, further cycles may be inserted to account for BusReleaseTime.
MemWait
Read
Read
Read data
Read data
Figure 9.4 Use of DataDriveDelay parameter
BusRelease
BusRelease
time
time
DataDriveDelay
Write data
Write
Write data
Write
Case 1. DataDriveDelay set
to zero. All dead time taken up
by BusReleaseTime.
Case 2. DataDriveDelay
used to absorb some
BusReleaseTime. Dead time
may be reduced.