st20-gp1 STMicroelectronics, st20-gp1 Datasheet - Page 108

• Manufacturer Part Number: st20-gp1
• Description: Gps Processor
• Manufacturer: STMicroelectronics

ST20-GP1
19.5.2 Valid/Ack protocol
In this mode the two control pins PlinknotReq (Qack/Ivalid) and PlinknotAck (Qvalid/Iack) are
active high. The initial (inactive) state of the two control wires is low.
108/116
PLink is output
PLink is input
PlinknotAck
(Qvalid)
PlinknotReq
(Qack)
PlinkData0-7
PlinknotReq
(Ivalid)
PlinknotAck
(Iack)
PlinkData0-7
Figure 19.7 Byte-wide parallel port timings when using the Valid/Ack protocol
Symbol Parameter
t
t
t
t
t
t
t
t
t
t
t
PAHPRH
DOVPAH
PRHPAL
PALPRL
PRLDOX
DIVPRH
PAHDIX
PAHPRL
PRLPAH
PRLPAL
PALPRH
old data
PlinknotAck rising transition to PlinknotReq rising
PlinkData0-7 setup time before rising edge of PlinknotAck
PlinknotReq rising edge to PlinknotAck falling edge
PlinknotReq falling edge after PlinknotAck falling edge
PlinkData0-7 hold time after PlinknotReq falling edge
(i.e. before new data may be put onto bus)
PlinkData setup time before PlinknotReq rising edge
PlinkData hold after PlinknotAck rising edge
PlinknotReq falling edge after PlinknotAck rising edge
PlinknotReq falling edge to PlinknotAck rising edge
PlinknotAck falling edge after PlinknotReq falling edge
PlinknotReq rising edge after PlinknotAck falling edge
t
DOVPRH
Table 19.6 Timings for Valid/Ack protocol
t
DOVPAH
t
PRLPAH
t
PAHPRH
t
PAHDIX
ST20 Output
ST20 Input
t
PAHPRL
t
PRHPAL
valid data
t
PRLPAL
t
PALPRL
t
PALPRH
t
PRLDOX
Min
40
0
0
0
0
0
0
0
0
0
0
Max
300
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns