st20-gp1 STMicroelectronics, st20-gp1 Datasheet - Page 31

• Manufacturer Part Number: st20-gp1
• Description: Gps Processor
• Manufacturer: STMicroelectronics

5.6
The interrupt controller is allocated a 4k block of memory in the internal peripheral address space.
Information on interrupts is stored in registers as detailed in the following section. The registers can
be examined and set by the devlw (device load word) and devsw (device store word) instructions.
Note, they can not be accessed using memory instructions.
HandlerWptr register
The HandlerWptr registers (1 per interrupt) contain a pointer to the workspace of the interrupt
handler.
Note, before the interrupt is enabled, by writing a 1 in the Mask register, the user (or toolset) must
ensure that there is a valid Wptr in the register.
TriggerMode register
Each interrupt channel can be programmed to trigger on rising/falling edges or high/low levels on
the external Interrupt.
Note, level triggering is different to edge triggering in that if the input is held at the triggering level, a
continuous stream of interrupts is generated.
Mask register
An interrupt mask register is provided in the interrupt controller to selectively enable or disable
external interrupts. This mask register also includes a global interrupt disable bit to disable all
external interrupts whatever the state of the individual interrupt mask bits.
To complement this the interrupt controller also includes an interrupt pending register which
contains a pending flag for each interrupt channel. The Mask register performs a masking function
on the Pending register to give control over what is allowed to interrupt the CPU while retaining the
ability to continually monitor external interrupts.
HandlerWptr0-4
Bit
31:2
1:0
TriggerMode0-4
Bit
2:0
Interrupt configuration registers
Bit field
HandlerWptr
Bit field
Trigger
Table 5.1 HandlerWptr register format — one register per interrupt
Table 5.2 TriggerMode register format — one register per interrupt
Interrupt controller base address + #00 to #10
Interrupt controller base address + #40 to #50
Function
Pointer to the workspace of the interrupt handler.
RESERVED. Write 0.
Function
Control the triggering condition of the Interrupt, as follows:
Trigger2:0
000
001
010
011
100
101
110
111
Interrupt triggers on
No trigger mode
High level - triggered while input high
Low level - triggered while input low
Rising edge - low to high transition
Falling edge - high to low transition
Any edge - triggered on rising and falling edges
No trigger mode
No trigger mode
Read/Write
Read/Write
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