st20-gp1 STMicroelectronics, st20-gp1 Datasheet - Page 60

• Manufacturer Part Number: st20-gp1
• Description: Gps Processor
• Manufacturer: STMicroelectronics

ST20-GP1
The behavior of the ST20-GP1 after reset depends upon the value on the BootSource0-1 pins. In
all cases, the EMI is loaded with a slow default configuration which is suitable for performing
accesses to ROM and SRAM (see Figure 9.7).
When booting from ROM, the first EMI access will be an instruction fetch from bank 3. When
booting from a link, the bootstrap is loaded into the ST20-GP1 internal SRAM located logically at
the bottom of bank 0.
The default bus width for all banks is set at reset by reading the value on the BootSource0-1 pins
(see Table 9.1). If this bus width is inappropriate for a particular bank, then configuration software
must change it before it is accessed, otherwise some memory locations will contain indeterminate
contents. Note, particular care must be paid to instruction fetching behavior of the CPU. It is
important to match the program memory with the correct bus width using BootSource0-1.
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Parameter
BusWidth
MemWaitEnable
BankReadOnly
AccessDuration
CEe1Time
CEe2Time
OEe1Time
WBe1Time
WBe2Time
BusReleaseTime
DataDriveDelay
notMemWB0-1
MemAddr1-19
MemData0-15
MemData0-15
notMemOE
notMemCE
(write)
(read)
Table 9.9 Configuration register values during reset
Bits
1
1
1
4
4
4
4
4
4
2
3
9 phases (4.5 cycles)
5 phases
Value during and after reset
Depends on BootSource0-1 pins (see Table 9.1, page 52).
1 (Enabled)
0 (Read/Write)
1010 (10 cycles)
0000
0000
0000
1001 (9 phases; 4.5 cycles)
0010 (2 phases; 1 cycle)
10 (2 cycles)
101 (5 phases; 2.5 cycles)
Figure 9.7 Default configuration
10 cycles
2 phases (1 cycle)
2 cycles
Units
Cycles
Phases
Phases
Phases
Phases
Phases
Cycles
Phases
-
-
-