st20-gp1 STMicroelectronics, st20-gp1 Datasheet - Page 50

• Manufacturer Part Number: st20-gp1
• Description: Gps Processor
• Manufacturer: STMicroelectronics

ST20-GP1
9
The ST20-GP1 programmable memory interface provides glueless support for up to four banks of
SRAM or ROM memory. Sufficient configuration options are provided to enable the interface to be
used with a wide variety of SRAM speeds, permitting systems to be built with optimum price/
performance trade-offs.
Although designed primarily for SRAM-like memory devices, the configurability enables glueless
connection to other peripheral devices such as FIFOs and UARTs.
The programmable memory interface is also referred to as the external memory interface (EMI).
The EMI provides configuration information for four independent banks of external memory
devices. The addresses of these bank boundaries are hard wired to give each bank one quarter of
the address space of the machine. Bank 0 occupies the lowest quarter of the [signed] address
space, bank 3 is the highest, see Figure 9.1. Each bank can contain up to 1 Mbyte of external
memory.
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Programmable memory interface
Addresses shown are physical addresses.
7FFFFFFF
40000000
3FFFFFFF
20000000
1FFFFFFF
00000000
FFFFFFFF
C0000000
BFFFFFFF
80000000
On-chip peripheral
Internal SRAM
registers
Figure 9.1 Memory allocation
On-chip peripheral registers (including the EMI
configuration registers) are mapped into the upper
half of this bank.
Subsystem
exceptions
channels
Internal
SRAM
Traps/
80000FFF
MemStart
80000000