st20-gp1 STMicroelectronics, st20-gp1 Datasheet - Page 61

• Manufacturer Part Number: st20-gp1
• Description: Gps Processor
• Manufacturer: STMicroelectronics

10 Clocks and low power controller
10.1 Clocks
An on-chip phase locked loop (PLL) generates all the internal high frequency clocks. The PLL is
used to generate the internal clock frequencies needed for the CPU and the Link. Alternatively a
direct clock input can provide the system clocks. The single clock input (ClockIn) must be
16.368 MHz for PLL operation for GPS.
The internal clock may be turned off (including the PLL) enabling power down mode.
The ST20-GP1 can be set to operate in TimesOneMode, which is when the PLL is bypassed.
During TimesOneMode the input clock must be in the range 0 to 30 MHz and should be nominally
50/50 mark space ratio.
10.1.1 Speed select
The speed of the internal processor clock is variable in discrete steps. The clock rate at which the
ST20-GP1 runs is determined by the logic levels applied on the two speed select lines
SpeedSelect0-1 as detailed in Table 10.1. The frequency of ClockIn (fclk) for the speeds given in
the table is 16.368 MHz.
The SysRatio register, see Table 10.9, gives the speed at which the system PLL is running. It
contains the relevant PLL multiply ratio when using the PLL, or contains the value ‘1’ when in
TimesOneMode for the PLL.
10.2 Low power control
The ST20-GP1 is designed for 0.5 micron, 3.3V CMOS technology and runs at speeds of up to
32.736 MHz. 3.3V operation provides reduced power consumption internally and allows the use of
low power peripherals. In addition, to further enhance the potential for battery operation, a low
power power-down mode is available.
The different power levels of the ST20-GP1 are listed below.
SpeedSelect1
•
•
•
0
0
1
1
Operating power — power consumed during functional operation.
Stand-by power — power consumed during little or no activity. The CPU is idle but ready to
immediately respond to an interrupt/reschedule.
Power-down — internal clocks are stopped and power consumption is significantly reduced.
Functional operation is stalled. Normal functional operation can be resumed from previous
SpeedSelect0
0
1
0
1
Table 10.1 Processor speed selection
Processor clock
speed (MHz)
16.368
32.736
TimesOneMode
cycle time (ns)
approximate
RESERVED
Processor
61.0
30.5
Phase lock loop
factor (PLLx)
1
2
Link speed
(Mbits/s)
0.4 x fclk
ST20-GP1
19.641
19.641
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