st20-gp1 STMicroelectronics, st20-gp1 Datasheet - Page 29

• Manufacturer Part Number: st20-gp1
• Description: Gps Processor
• Manufacturer: STMicroelectronics

5.1
The interrupt controller contains a table of pointers to interrupt handlers. Each interrupt handler is
represented by its workspace pointer (Wptr). The table contains a workspace pointer for each level
of interrupt.
The Wptr gives access to the code, data and interrupt save space of the interrupt handler. The
position of the Wptr in the interrupt table implies the priority of the interrupt.
Run-time library support is provided for setting and programming the vector table.
5.2
At any interruptible point in its execution the CPU can receive an interrupt request from the
interrupt controller. The CPU immediately acknowledges the request.
In response to receiving an interrupt the CPU performs a procedure call to the process in the
vector table. The state of the interrupted process is stored in the workspace of the interrupt handler
as shown in Figure 5.2. Each interrupt level has its own workspace.
The interrupt routine is initialized with space below Wptr. The Iptr and Status word for the routine
are stored there permanently. This should be programmed before the Wptr is written into the vector
table. The behavior of the interrupt differs depending on the priority of the CPU when the interrupt
occurs.
When an interrupt occurs when the CPU was running at high priority, the CPU saves the current
process state (Areg, Breg, Creg, Wptr, Iptr and Status) into the workspace of the interrupt
handler. The value HandlerWptr, which is stored in the interrupt controller, points to the top of this
Wptr
Interrupt vector table
Interrupt handlers
Handler Status
Before interrupt
Handler Iptr
Figure 5.2 State of interrupted process
Wptr
Interrupting high priority
Handler Status
Handler Iptr
process
Status
Creg
Breg
Areg
Wptr
Iptr
Wptr
Interrupting low priority
process or CPU idle
Handler Status
Handler Iptr
Null Status
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