st20-gp1 STMicroelectronics, st20-gp1 Datasheet - Page 74

• Manufacturer Part Number: st20-gp1
• Description: Gps Processor
• Manufacturer: STMicroelectronics

ST20-GP1
9-bit data frames
9-bit data frames consist of:
Parity may be odd or even, depending on the ParityOdd bit in the ASCControl register. An even
parity bit will be set, if the modulo-2-sum of the eight data bits is 1. An odd parity bit will be cleared
in this case. The parity error flag (ParityError) will be set if a wrong parity bit is received. The parity
bit itself will be stored in bit 8 of the ASCRxBuffer register, see Table 13.4.
In wake-up mode, received frames are only transferred to the receive buffer register if the ninth bit
(the wake-up bit) is 1. If this bit is 0, no receive interrupt request will be activated and no data will
be transferred. This feature can be used to control communication in multi-processor systems.
When the master processor wants to transmit a block of data to one of several slaves, it first sends
out an address byte which identifies the target slave. An address byte differs from a data byte in
that the additional ninth bit is a 1 for an address byte and a 0 for a data byte, so no slave will be
interrupted by a data byte. An address byte will interrupt all slaves (operating in 8-bit data + wake-
up bit mode), so each slave can examine the 8 least significant bits (LSBs) of the received
character (the address). The addressed slave will switch to 9-bit data mode, which enables it to
receive the data bytes that will be coming (with the wake-up bit cleared). The slaves that are not
being addressed remain in 8-bit data + wake-up bit mode, ignoring the following data bytes.
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nine data bits D0-8;
eight data bits D0-7 plus an automatically generated parity bit;
eight data bits D0-7 plus a wake-up bit.
start
bit
(LSB)
D0
D1
D2
Figure 13.2 8-bit data frames
D3
D4
D5
D6
Data bit (D7)
Parity bit
8th
bit
stop
1st
bit
stop
2nd
bit