st20-gp1 STMicroelectronics, st20-gp1 Datasheet - Page 88

• Manufacturer Part Number: st20-gp1
• Description: Gps Processor
• Manufacturer: STMicroelectronics

ST20-GP1
15 Byte-wide parallel port
The byte-wide parallel port is provided to drive an external device using 8-bit half-duplex streamed
I/O and two control wires.
The byte-wide parallel port has 2 modes of operation, as follows:
The mode of operation is determined by the setting of the configuration registers, see Section 15.3.
15.1 EMI mode operation
In this mode the EMI is in total control of the PlinkData0-7 pins. The PlinknotAck output is forced
to its ‘inactive’ state during this mode.
The interface to the external device is controlled by the EMI. The bottom 8 bits of the EMI data bus
(MemData0-7) are redirected (copied) to the PlinkData0-7 pins. The direction of these pads is
controlled by the EMI. The external timing and data transfer of this activity is controlled by the
programmed configuration of the EMI bank 2 (see Section 9.5 on page 58).
15.2 Parallel link (DMA) mode operation
In this mode the byte-wide parallel port is a DMA (direct memory access) engine which performs
memory transfers to and from the external links on behalf of a controller (the CPU). The parallel link
is unidirectional and only transfers data in one direction across the memory bus at any given time.
The byte-wide parallel port defaults to input (to the ST20-GP1) when the ST20-GP1 is reset (with
the notRST pin) to prevent contention, and can be used for DMA functions without interfering with
memory bank 2. However to access external registers via the PlinkData0-7 pins, the bit in the
PlinkEmi register (see Table 15.1) must be set by software. This results in all accesses to external
memory bank 2 being diverted via the port rather than MemData0-7, allowing both register and
DMA access to the external peripheral. External memory bank 2 must be dedicated solely for this
use while the register access of this external peripheral is enabled.
Being half-duplex, the direction of the link when in DMA mode must be selected in software by
setting the bit in the PlinkIO register (see Table 15.2 below). Data transfer for the parallel port (for
DMA transfers) occur by the use of a channel. When the EMI is using these pads the directionality
is controlled by the EMI and not the DMA control register.
15.3 Configuration registers
There are three control registers for the parallel port which are programmed by use of devsw
(device store) and devlw (device load) instructions. The base address for the parallel port
configuration registers is given in the Memory Map chapter.
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it can operate as an ASIC interface. In this mode the external data transfer is controlled by
the EMI strobes and addresses.
it can operate as a byte-wide parallel link (PLink) using an external asynchronous transfer
mechanism to control transfers.