st20-gp1 STMicroelectronics, st20-gp1 Datasheet - Page 76

• Manufacturer Part Number: st20-gp1
• Description: Gps Processor
• Manufacturer: STMicroelectronics

ST20-GP1
For 1.5 stop bits, the majority decision of the fifteenth, sixteenth, and seventeenth samples during
the stop bits is used to determine the effective stop bit value.
When the last stop bit has been received (at the end of the last programmed stop bit period) the
content of the receive shift register is transferred to the receive data buffer register
(ASCRxBuffer). The receive buffer full flag (RxBufFull) is set, and the parity (ParityError) and
framing error (FrameError) flags are updated, after the last stop bit has been received (at the end
of the last stop bit programmed period), regardless of whether valid stop bits have been received or
not. The receive circuit then waits for the next start bit (falling edge transition) at the RXD pin.
Reception is stopped by clearing the RxEnable bit. A currently received frame is completed
including the generation of the receive status flags. Start bits that follow this frame will not be
recognized.
Note: In wake-up mode, received frames are only transferred to the receive buffer register if the ninth
bit (the wake-up bit) is 1. If this bit is 0, the receive buffer full (RxBufFull) flag will not be set and no
data will be transferred.
13.2 Hardware error detection capabilities
To improve the safety of serial data exchange, the ASC provides three error status flags in the
ASCStatus register which indicate if an error has been detected during reception of the last data
frame and associated stop bits.
The parity error (ParityError) bit is set when the parity check on the received data is incorrect.
The framing error (FrameError) bit is set when the RXD pin is not a 1 during the programmed
number of stop bit times, sampled as described in the section above.
The overrun error (OverrunError) bit is set when the last character received in the ASCRxBuffer
register has not been read out before reception of a new frame is complete.
These flags are updated simultaneously with the transfer of data to the receive buffer.
13.3 Baud rate generation
The ASC has its own dedicated 16-bit baud rate generator with 16-bit reload capability.
The baud rate generator is clocked with the CPU clock. The timer counts downwards and can be
started or stopped by the Run bit in the ASCControl register. Each underflow of the timer provides
one clock pulse. The timer is reloaded with the value stored in its 16-bit reload register each time it
underflows. The ASCBaudRate register is the dual-function baud rate generator/reload register. A
read from this register returns the content of the timer, writing to it updates the reload register.
An auto-reload of the timer with the content of the reload register is performed each time the
ASCBaudRate register is written to. However, if the Run bit is 0 at the time the write operation to
the ASCBaudRate register is performed, the timer will not be reloaded until the first CPU clock
cycle after the Run bit is 1.
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