st20-gp1 STMicroelectronics, st20-gp1 Datasheet - Page 54

• Manufacturer Part Number: st20-gp1
• Description: Gps Processor
• Manufacturer: STMicroelectronics

ST20-GP1
Figure 9.3 shows the generic EMI activity during a write access. notMemOE is inactive during a
write access, and the function of notMemWB1 is dictated by the bus width of the bank in the same
way as for a read access. MemData8-15 is held in high impedance during a write access if the bus
width is 8-bit, otherwise it follows the timing configured for MemData0-7.
The following caveats relate to strobe edge programming:
Transactions normally consist of several accesses which run consecutively without any ‘dead
cycles’. The number of accesses in a transaction is dependent on the bus width and the nature of
the memory bus request. Table 9.3 lists the transaction composition and the behavior of
MemAddr1 and notMemWB0-1 for each access.
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If any of the strobe edges are programmed to occur outside the period defined by Access-
Duration, the activity for that strobe is undefined.
If a strobe’s rising and falling edges are programmed to occur on the same system clock
edge, they will nullify each other and the strobe will stay in the same state. This rule also
applies for consecutive accesses.
MemData8-15†
MemAddr1-19
notMemWB1*
notMemWB0
MemData0-7
(MemAddr0)
* Only when bus width is 8-bit. When bus width is 16-bit, notMemWB1 follows the timing
specified for notMemWB0.
† Held in high impedance when bus width is 8-bit.
notMemCE
Figure 9.3 Configuration parameters for a write access
CEe1 time
Data drive delay
WBe1 time
Access duration
CEe2 time
WBe2 time