st20-gp1 STMicroelectronics, st20-gp1 Datasheet - Page 73

• Manufacturer Part Number: st20-gp1
• Description: Gps Processor
• Manufacturer: STMicroelectronics

Eight or nine bit data transfer, parity generation, and the number of stop bits are programmable.
Parity, framing, and overrun error detection is provided to increase the reliability of data transfers.
Transmission and reception of data is double-buffered. For multiprocessor communication, a
mechanism to distinguish address from data bytes is included. Testing is supported by a loop-back
option. A 16-bit baud rate generator provides the ASC with a separate serial clock signal.
13.1 Asynchronous serial controller operation
The operating mode of the serial channel ASC is controlled by the control register (ASCControl).
This register contains control bits for mode and error check selection, and status flags for error
identification.
A transmission is started by writing to the transmit buffer register (ASCTxBuffer), see Table 13.3.
Data transmission is double-buffered, therefore a new character may be written to the transmit
buffer register, before the transmission of the previous character is complete. This allows
characters to be sent back-to-back without gaps.
Data reception is enabled by the receiver enable bit (RxEnable) in the ASCControl register. After
reception of a character has been completed the received data, and received parity bit if selected,
can be read from the receive buffer register (ASCRxBuffer), refer to Table 13.4.
Data reception is double-buffered, so the reception of a second character may begin before the
previously received character has been read out of the receive buffer register. The overrun error
status flag (OverrunError) in the status register (ASCStatus), see Table 13.7, will be set when the
receive buffer register has not been read by the time reception of a second character is complete.
The previously received character in the receive buffer is overwritten, and the ASCStatus register
is updated to reflect the reception of the new character.
The loop-back option (selected by the LoopBack bit) internally connects the output of the
transmitter shift register to the input of the receiver shift register. This may be used to test serial
communication routines at an early stage without having to provide an external network.
13.1.1 Data frames
Data frames are selected by the setting of the Mode bit field in the ASCControl register, see Table
13.5.
8-bit data frames
8-bit data frames consist of:
Parity may be odd or even, depending on the ParityOdd bit in the ASCControl register. An even
parity bit will be set, if the modulo-2-sum of the seven data bits is 1. An odd parity bit will be cleared
in this case. The parity error flag (ParityError) will be set if a wrong parity bit is received. The parity
bit itself will be stored in bit 7 of the ASCRxBuffer register.
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eight data bits D0-7;
seven data bits D0-6 plus an automatically generated parity bit.
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