MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 99

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

Address: 6002 (Hex)
Label: TIS
Reset Value: XX00
TDMSERV
CORSIGA
CORSIGB
CORSIGC
CORSIGD
CORSIGE
Reserved
Reserved
TRUCR
CFAIL
CABS
TRUE
Label
TOB
Position
Bit
3:0
10
11
12
13
14
15
4
5
6
7
8
9
R/O/L
R/O/L
R/O/L
R/O/L
R/O/L
Type
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
Table 48 - TDM Interface Status Register
Reserved. Always read as “0000”.
Clock Absent. This flag is raised when one or more of the three TDM clock pins (CLKX2,
CLKX1, and FSYNC) has not changed state within a specified number of MCLK cycles.
The signals are monitored when the pins are inputs (TDM Clock Slave or Clock Master
Alternate modes), and also when the pins are outputs (TDM Clock Master mode).
This flag is disabled when GENOE is LOW. Writing a ‘1’ over this bit clears it.
Note when TCLKSYN in register 6010h is set to ‘1’ in TDM Slave mode, the CLKx1 pin is
not used as an output but remains high-impedance. The CABS bit will therefore report a
loss of clocks unless an external signal is present at the CLKx1 pin.
SCSA Clock Fail. This flag is used only when the MT90500 is NOT the clock master (i.e.
configured as Slave or as Clock Master Alternate in SCSA mode). This flag is raised and
latched when the CLKFAIL pin is sampled HIGH and the CORSIGA pin is configured as
CLKFAIL input (i.e. CORSIGACNF in 6004h must be “11”). The CORSIGA bit in this
register can be used to verify the current state of the CLKFAIL signal.
When this bit is HIGH, and the CLK_ALT bit in 6010h is HIGH, the MT90500 will drive
the TDM clock lines (switch from Master Alternate to Master) and if CORSIGACNF is
“11”, drive 0 out on CORSIGA/CLKFAIL.
This flag is disabled when GENOE is LOW. Writing a ‘1’ over this bit clears it.
TDM Out of Bandwidth. This flag is raised when the internal to/from external memory
process is unable to transfer all the data in the specified time. This flag generally
indicates that there is a bandwidth limitation in accesses to external memory. External
memory access requirements must be reduced, or external memory speed must be
increased. The IEENA bit in the TDM Interface Control Register at 6000h must be set for
this error to be generated.
Writing a ‘1’ over this bit clears it.
TDM Read Underrun Error. ‘0’ = Error has not occurred. ‘1’ = An underrun has occurred.
Indicates the occurrence of an underrun on a TDM read from one of the Receive Circular
Buffers. This error-indication is controlled by the TDM Read Underrun Detection Enable
(U) bits in the External Memory to Internal TDM Memory Control Structure (i.e. if the U
bits are LOW, no underrun errors will be noted in this register).
Writing a ‘1’ over this bit clears it.
TDM Read Underrun Count Rollover. This flag is raised when the underrun counter at
register 6048h returns to 0000h. Writing a ‘1’ over this bit clears it.
TDM Service Bit. This bit is set if any of the above status bits<8:4> is set.
Reserved. Always read as ‘0’.
CORSIGA pin’s current logic level. Undefined at reset.
CORSIGB pin’s current logic level. Undefined at reset.
CORSIGC pin’s current logic level. Undefined at reset.
CORSIGD pin’s current logic level. Undefined at reset.
CORSIGE pin’s current logic level. Undefined at reset.
Description
MT90500
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