MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 137

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

7.
7.1
Figure 62 shows a general board level application for the MT90500. This shows a high-level view of the device
connection to external memory, a CPU, an ATM Physical Layer device, an ATM AAL5 SAR device, and the TDM
backplane.This is a general application diagram; the most frequent variations would be: the number and size of
the SSRAM chips, the type of CPU or PHY, the mode of the TDM backplane and TDM local bus (several
possibilities are listed in the figure), and the presence or absence of a secondary SAR.
The size of external memory is selected to suit the application, and is tied to the number of TDM 64 kbps
channels to be used, the number of VCs to be used, and the Cell Delay Variation tolerance of the receive
channels. Similarly the CPU and PHY are chosen to suit the application. The TDM backplane mode (positive or
negative frame-pulse; fast or slow hold time; and 2.048, 4.096, or 8.192 Mbps) is application selectable, and
the local TDM bus can be enabled for applications which require it (e.g. when it is desirable to have a local
HDLC, or DSP, which is not tied to the backplane). The secondary SAR may be used in applications which
require ATM signalling, though it is possible to do a moderate amount of signalling using the TX and RX Data
FIFOs in the MT90500, provided that the CPU can perform the rest of the SAR functions in software.
16-bit CPU port for
internal register and
external memory pro-
gramming
Applications
Board Level Applications
Off-the-shelf
ATM PHY
Device
CPU
Figure 62 - MT90500 Device Application Block Diagram
SAR Device
Off-the-shelf
(AAL5)
Primary
UTOPIA
Port
MT90500
Secondary
UTOPIA
Port
Local Memory
240-PQFP
TDM Data, Clock
and Sync Lines
External
Synchronous
SRAM
MVIP-90
H-MVIP
ST-BUS
SCSA
IDL
MT90500
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