MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 94

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

MT90500
5.2.4
94
Address: 4002 (Hex)
Label: USR
Reset Value: 0000 (Hex)
Address: 4000 (Hex)
Label: UCR
Reset Value: 0000 (Hex)
RXFFORIE
RXFFRCIE
RXFFENA
RXFFWP+
UTOSERV
Reserved
OAMSEL
RXBASE
STXENA
RXORIE
Reserved
Reserved
RXFFOR
RXFFRC
RXENA
UKSEL
TESTS
Label
RXOR
Label
RRP
UTOPIA Registers
Position
Position
14:13
9:7
14:13
Bit
10
11
12
15
0
1
2
3
4
5
6
Bit
9:0
10
12
15
11
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/O/L
R/O/L
R/O/L
Type
R/O
R/O
R/O
Table 34 - UTOPIA Control Register
Table 35 - UTOPIA Status Register
RX Cell Enable. When ‘0’, all received cells are ignored. When ‘1’, received cells are
processed normally.
Secondary TX Cell Enable. When this bit is ‘0’, no cells may be received from the
secondary TX interface. When ‘1’, the UTOPIA module receives cells from the secondary
SAR normally.
Round-Robin Priority. When ‘0’, CBR traffic from the MT90500 has priority over traffic from
the secondary SAR interface. When ‘1’, both traffic types have the same priority.
Receive FIFO Enable. When this bit is LOW, the Receive Data Cell FIFO Write Pointer
(RXFFWP at 4022h) is reset to 00h. When this bit is HIGH, the FIFO can operate normally.
Increment Receive Data Cell FIFO Write Pointer. When ‘1’ is written on this bit, the
Receive Data Cell FIFO Write Pointer (RXFFWP at 4022h) is incremented. Used for test
purposes only.
OAM Routing Select. ‘0’ = discard; ‘1’= treat as non-CBR data cell.
Unknown Routing Select. ‘0’ = discard cells with undefined entry types (i.e. T bits = “00” in
look-up table); ‘1’= treat cells with undefined entry types (i.e. T bits = “00” in look-up table)
as non-CBR data cells.
RX Control Structure Base Address. These three bits represent the three most significant
address bits<20:18> of the pointer to the Receive Control Structures.
Receive Data Cell FIFO Overrun Error Interrupt Enable. ‘0’ = Disabled; ‘1’ = Enabled.
When enabled, a ‘1’ on RXFFOR in Register 4002h will force a ‘1’ on MUX_SERV in
Register 0002h.
RX UTOPIA Module Internal FIFO Overrun Interrupt Enable. ‘0’ = Disabled; ‘1’ = Enabled.
When enabled, a ‘1’ on RXOR in Register 4002h will force a ‘1’ on MUX_SERV in Register
0002h.
Receive Data FIFO Receive Cell Interrupt Enable. ‘0’ = Disabled; ‘1’ = Enabled. When
enabled, a ‘1’ on RXFFRC in Register 4002h will force a ‘1’ on MUX_SERV in Register
0002h.
Reserved. Should be written as “00”.
TEST Status. When HIGH, this bit forces the three status events (bits<12:10>) in the
UTOPIA Status Register at 4002h to occur. Used for test purposes only.
Reserved. Always read as “00_0000_0000”.
Receive Data Cell FIFO Overrun Error. When this bit is ‘1’, the RXFFWP (register 4022h) =
RXFFRP (register 4024h) and one or more non-CBR data cells were discarded because
the Receive Data Cell FIFO was full. Writing a ‘1’ over this bit clears it.
Receive UTOPIA Module Internal FIFO Overrun. At least one CBR cell was lost because
the RX_SAR did not process the cells fast enough. Writing a ‘1’ over this bit clears it.
Data FIFO Receive Cell. Each time a non-CBR data cell is received, this bit is set. Writing
a ‘1’ over this bit clears it.
Reserved. Always read as “00”.
UTOPIA Service. When any of the status bits in this register are HIGH, this bit is HIGH.
Description
Description