MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 91

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

5.2.3
Address: 3000 (Hex)
Label: RXSCR
Reset Value: 0000 (Hex)
WURCRIE
WORCRIE
POREMS
WUREIE
WOREIE
POREIE
APEMS
ACEMS
SNEMS
PPEMS
MCRIE
TESTS
ACEIE
SNEIE
APEIE
PPEIE
Label
RX_SAR Registers
Bit Position
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 26 - RX_SAR Control Register
AAL1-byte Parity Error Misc. Select. When this bit is set, a parity error in the AAL1-byte
increments the RX_SAR Misc. Event Counter Register (3012h) and affects the RX_SAR
Misc. Event ID Register (3010h).
AAL1-byte CRC Error Misc. Select. When this bit is set, a CRC error in the AAL1-byte
increments the RX_SAR Misc. Event Counter Register (3012h) and affects the RX_SAR
Misc. Event ID Register (3010h).
AAL1 Sequence Number Error Misc. Select. When this bit is set, a sequence number error
in the AAL1-byte increments the RX_SAR Misc. Event Counter Register (3012h) and
affects the RX_SAR Misc. Event ID Register (3010h).
Pointer-byte Parity Error Misc. Select. When this bit is set, a parity error in the pointer-byte
(for P-Type cells only) increments the RX_SAR Misc. Event Counter Register (3012h) and
affects the RX_SAR Misc. Event ID Register (3010h).
Pointer-byte Out of Range Error Misc. Select. When this bit is set, an out of range pointer-
byte (for P-Type cells only) increments the RX_SAR Misc. Event Counter Register (3012h)
and affects the RX_SAR Misc. Event ID Register (3010h).
AAL1-byte Parity Error Interrupt Enable. ‘0’ = Disabled; ‘1’ = Enabled. When enabled, a ‘1’
on APE in Register 3002h will force a ‘1’ on RX_SAR_SERV in Register 0002h.
AAL1-byte CRC Error Interrupt Enable. ‘0’ = Disabled; ‘1’ = Enabled. When enabled, a ‘1’
on ACE in Register 3002h will force a ‘1’ on RX_SAR_SERV in Register 0002h
AAL1-byte Sequence Number Error Interrupt Enable. ‘0’ = Disabled; ‘1’ = Enabled. When
enabled, a ‘1’ on SNE in Register 3002h will force a ‘1’ on RX_SAR_SERV in Register
0002h
Pointer-byte Parity Error Interrupt Enable. ‘0’ = Disabled; ‘1’ = Enabled. When enabled, a
‘1’ on PPE in Register 3002h will force a ‘1’ on RX_SAR_SERV in Register 0002h
Pointer-byte Out of Range Error Interrupt Enable. ‘0’ = Disabled; ‘1’ = Enabled. When
enabled, a ‘1’ on PORE in Register 3002h will force a ‘1’ on RX_SAR_SERV in Register
0002h
Write Underrun Error Interrupt Enable. ‘0’ = Disabled; ‘1’ = Enabled. When enabled, a ‘1’
on WURE in Register 3002h will force a ‘1’ on RX_SAR_SERV in Register 0002h
Write Overrun Error Interrupt Enable. ‘0’ = Disabled; ‘1’ = Enabled. When enabled, a ‘1’ on
WORE in Register 3002h will force a ‘1’ on RX_SAR_SERV in Register 0002h
Misc. Counter Rollover Interrupt Enable. ‘0’ = Disabled; ‘1’ = Enabled. When enabled, a ‘1’
on MCR in Register 3002h will force a ‘1’ on RX_SAR_SERV in Register 0002h
Write UnderRun Counter Rollover Interrupt Enable. ‘0’ = Disabled; ‘1’ = Enabled. When
enabled, a ‘1’ on WURCR in Register 3002h will force a ‘1’ on RX_SAR_SERV in Register
0002h
Write Overrun Counter Rollover Interrupt Enable. ‘0’ = Disabled; ‘1’ = Enabled. When
enabled, a ‘1’ on WORCR in Register 3002h will force a ‘1’ on RX_SAR_SERV in Register
0002h
Test Status. When HIGH, this bit forces all the status events in the RX_SAR Status
Register at 3002h to occur. Also increments the RX_SAR Misc. Event Counter Register
(3012h), the RX_SAR Underrun Event Counter (3022h), and the RX_SAR Overrun Event
Counter (3032h) and affects the contents of the RX_SAR Misc. Event ID Register (3010h),
the RX_SAR Underrun Event ID Register (3020h), and the RX_SAR Overrun Event ID
Register (3030h). Used for test purposes only.
Description
MT90500
91