MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 75
MT90500
Manufacturer Part Number
MT90500
Description
Multi-Channel ATM AAL1 SAR
Manufacturer
Mitel Semiconductor
Datasheet
1.MT90500.pdf
(159 pages)
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Note 1: In ATM receive applications, SRTSDATA corresponds to the 4-bit SRTS calculated
as the difference between the locally-generated RTS code and the remotely-generated RTS
code received from the incoming ATM cell stream.
Note 2: The external timing generation logic generates an 8 kHz output reference clock. This
signal is fed from the FPGA into the EX_8KA input of the MT90500 to be routed back to the
external PLL.
Note 3: The external reference timing generation logic can be implemented in a small FPGA.
.
TDM Port
Figure 35 - Clock Recovery Using SRTS Method (Hardware)
SRTSDATA
CLKx1
FSYNC
MT90500
DEVICE
CORSIGD
UTOPIA interface
EXTERNAL LOCAL
REFERENCE TIMING
GENERATION
CIRCUIT (Small FPGA)
CORSIGC
ATM PHY
DEVICE
SRTSENA
REF8KCLK
CORSIGB
EX_8KA
PLLCLK
Network Reference Clock
FNXI
Divide by x
e.g. MT9041
PLL
MT90500
75
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