MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 42

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

MT90500
4.3
4.3.1
4.3.1.1
The TX_SAR block is responsible for performing CBR (Constant Bit Rate) cell assembly functions from the
TDM port towards the ATM Primary UTOPIA interface, which is typically connected to a PHY device. According
to a user-programmable timing algorithm, the TX_SAR circuit fetches data from the Transmit Circular Buffers
located in external memory and builds CBR ATM cells (AAL1, CBR-AAL0, or CBR-AAL5) which are
subsequently transferred to the MT90500 internal UTOPIA module and then to the Primary UTOPIA port. The
TX_SAR block has no direct interface to the pins of the MT90500, but ties together the TDM module and the
UTOPIA module. To construct CBR ATM cells, which must be periodically formed at the correct rate, an “event
scheduler” is used. To support different cell payload lengths and CBR AAL types, three programmable event
schedulers are provided by the TX_SAR to manage the cell transmission timing.
The TX_SAR provides enough bandwidth to allow the transmission of 1024 channels. The RX_SAR allows
reception of 1024 channels simultaneously. (For a total device capacity of 1024 bidirectional channels - all
2048 TDM time slots.)
The amount of external memory required to support the TX_SAR process depends on the number of TDM time
slots that need to be transmitted, as well as the number of simultaneous VCs. For example, the transmission of
1024 time slots over 1024 simultaneous VCs requires up to 100 Kbytes of external memory for the TX_SAR
process. Less memory is required if fewer VC connections or fewer TDM time slots are used.
4.3.1.2
The AAL1 cell generation process supports TDM transport and trunking over standardized SDT (Structured
Data Transfer) with pointer bytes for up to n = 122 TDM channels; over pointerless Structured Data Transfer for
42
TX_SAR Module
TX_SAR Overview
General
Supported ATM Cell Formats
Parity
Even
CSI
8
GFC / VPI
7
Sequence
VCI
Cell with Pointer
46 Payload Bytes
VPI
Count
6
Payload Byte #45
Payload Byte #46
Payload Byte #1
Payload Byte #2
5
Pointer
HEC
VCI
4
Figure 12 - AAL1 ATM Cell Format
PTI
CRC
field
3
VCI
VPI
2
Parity
Even
CLP
1
CSI
8
GFC / VPI
7
Cell without Pointer
VPI
VCI
Sequence
47 Payload Bytes
Count
6
Payload Byte #46
Payload Byte #47
Payload Byte #1
Payload Byte #2
Payload Byte #3
5
HEC
VCI
4
PTI
CRC
field
3
VCI
VPI
2
Parity
Even
CLP
1