MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 70

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

MT90500
4.6
4.6.1
Adaptive Clock Recovery is a flexible method for TDM clock recovery from an ATM link. There are several
approaches to adaptive clock recovery, and the standards do not require a specific one, so adaptive clock
recovery is termed “non-standardized.” The implementation given here is similar to the general outline in ITU-T
I.363.1. In the MT90500, adaptive clock recovery uses a reference 8 kHz clock to generate the TDM clock
signals. The TDM clocks are controlled by adjusting the reference 8 kHz clock frequency according to the
arrival rate of ATM cells on a designated VC.
As seen in Figure 31, the reception rate of timing reference cells or 8 kHz markers (EX_8KA) is used as the
basis for the adaptive clock recovery scheme implemented by this sub-module. This block is responsible for
generating (under software control) a reference clock signal (RXVCLK) based on the rate of reception of the
timing reference cells or markers. The sub-module additionally implements a state machine (seen in Figure 32)
which tracks the cell arrival rate, checks the cell sequence numbers for lost or misinserted cells or cells with
bad SNP fields (to a maximum of one), and adjusts for discrepancies.
The Adaptive Clock Recovery Block consists of:
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EX_8KA
CLKx1
MCLK
a Timing Reference Cell Processing unit which generates an event (“new_cell”) every time a timing
reference cell is received. A timing reference cell is defined as an AAL1 cell whose VPI/VCI matches
that specified in the VPI Timing Register (401Ah) and the VCI Timing Register (401Ch). OAM cells on
the specified VPI/VCI are ignored, as they do not carry CBR data. The unit can compensate for a single
lost or misinserted cell or bad sequence number protection (SNP). It will also flag an out-of-sync error
when more than one cell is lost, misinserted, or received with corrupted sequence number protection.
SNP-checking is enabled by setting the Seq_CRC_Ena bit in the Timing Reference Processing Control
Register at 60A0h. If no timing reference cell is received within a certain period (user-definable by
setting bits<9:0> in the same register), it will generate a loss of timing reference cell error. The state
machine for this unit is shown in Figure 32:
Clock Recovery from ATM Link
Adaptive Clock Recovery Sub-Module
Figure 31 - Adaptive Clock Recovery Sub-Module (Simplified Functional Block Diagram)
designated
timing VC
Timing Reference
Cell Processing
new_cell
EX_8KA
CLKx2
CLKx1
DIVX Ratio Register (60AAh)
Cell / 8 kHz
DIV 8
DIVX Register (60A8h)
1
0
External PLL
Event Counter
Temp Register
Counter
8 kHz
CNTUPDATE
RXVCLK
REFSEL<1:0> = 01
Register (60A2h)
Registers (60A4h
CLKx1 Count
Event Count
and 60A6h)
MT90500
REF8KCLK