MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 153

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

The above maximum requirement defines the theoretical minimum clock frequency the design must achieve to
support 1024 X 64 kbps bidirectional channels with 1024 VCs. Assuming a 29% margin for CPU accesses,
AAL0 cell processing, and random lost memory access efficiency, the MT90500 should be supplied with a
master clock (MCLK) of 60 MHz to support 1024 X 64 kbps bidirectional channels with 1024 VCs. It is also
recommended to select SSRAM to minimize turnaround cycles, for the greatest memory efficiency.
7.5
Delay through the MT90500, from TDM bus to TDM bus, depends on a number of variables, not all of which are
under the control of the designer. The following discussion omits ATM network delay (transmission delay), TDM
switching delay (caused by moving a TDM channel from time slot 0 to time slot 32, for instance) and CDV buffer
delay (Avg. Lead of the RX Circular Buffer). An example of large delay would use AAL1, N=1, fully-filled cells,
the delay for which can be typically 66 frames (8.25 msec). This is due to the following factors:
Minimum delay is achieved using larger trunking numbers (N > 47) or using partially filled cells with N = partial-
fill- level. Delay in this case will be 3 msec to 5 msec, with CDV buffers set to the minimum.
To these numbers, the designer may wish to add the application-specific delays: ATM network transmission
delay, ATM switching delay, CDV buffer delay, and TDM switching delay.
CBR Throughput Delay
----
47 frames cell assembly (47 byte payload)
66 frames
4
3
8
4
frames TX TDM Input Frame Buffer
frames average TX offset (TDM Write Pointer to TX_SAR Read Pointer)
frames RX Circular Buffer delay (Avg. Lead = 02h, = 8 frames)
frames RX TDM Output Frame Buffer.
MT90500
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