MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 19

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

3.
I/O types are: Output (O), Input (I), Bidirectional (I/O), Power (PWR), or Ground (GND).
Input pad types are: TTL, CMOS, Differential, or Schmitt. The notations “PU” and “PD” are used, respectively,
to indicate that a pad has an internal pullup or pulldown resistor. TTL (5V) inputs are pulled-up to the 5V rail,
CMOS (3.3V) inputs are pulled-up to the 3.3V rail. These weak internal resistors should not be relied upon for
fast data transitions. The 3.3V CMOS inputs have a switching threshold of 1.6V, and tolerate input levels of up
to 5V; therefore they are 5V TTL compatible (with the exception of the TRISTATE pin, which is not 5V tolerant).
Output pad types are generally described by voltage and current capability. Output types used are: 3.3V, 4mA;
5V, 4mA; 5V, 12mA; and open-drain. A notation of “SR” indicates that the pad is slew-rate limited. 3.3V CMOS
outputs will satisfy 5V TTL input thresholds at the rated current.
Refer to Figure 63 on page 139 for implementation details regarding the interface between two MT90500s and an external AAL5 SAR.
49, 48, 47, 46,
57, 58, 59, 62,
45, 44, 39, 38
63, 64, 65, 66
Pin #
52
51
53
82
50
56
55
54
79
Pin Descriptions
PRXDATA[7:0]
PTXDATA[7:0]
PRXCLAV
Pin Name
PTXCLAV
PRXSOC
PTXSOC
PTXPAR
PRXCLK
PTXCLK
PRXEN
PTXEN
I/O
I/O
O
O
O
O
I
I
I
I
I
I
TTL PU /
5V, 4mA
5V, 4mA
5V, 4mA
5V, 4mA
5V, 4mA
Table 1 - Primary UTOPIA Bus Pins
TTL PU
TTL PU
TTL PU
TTL PU
TTL PU
TTL PU
Type
SR
Primary UTOPIA transmit data bus. Byte-wide data driven from MT90500 to PHY
device. Bit 7 is the MSB.
Primary UTOPIA transmit start of cell signal. Asserted by the MT90500 when
PTXDATA[7:0] contains the first valid byte of the cell.
Primary UTOPIA transmit data enable. Active LOW signal asserted by the
MT90500 during cycles when PTXDATA[7:0] contains valid cell data.
Primary UTOPIA transmit cell available indication signal. For cell level flow
control, PTXCLAV is asserted by the PHY to indicate to the MT90500 that the
PHY can accept the transfer of a complete cell.
Primary UTOPIA transmit clock. Data transfer & synchronization clock provided by
the MT90500 to the PHY for transmitting data on PTXDATA[7:0]; software
configurable (in Main Control Register at 0000h) to run at up to 25 MHz. Note that
this pin should be configured as an output for exact compliance with UTOPIA
Level 1, V2.01.
Primary UTOPIA transmit parity. This signal is the odd parity bit over
PTXDATA[7:0].
Primary UTOPIA receive data bus. Byte-wide data driven from the PHY to the
MT90500. PRXDATA[7] is the MSB.
Primary UTOPIA receive start of cell signal. Asserted by the PHY when
PRXDATA[7:0] contains the first valid byte of a cell.
Primary UTOPIA bus data enable. Active LOW signal normally asserted by the
secondary SAR to indicate that PRXDATA[7:0], PRXSOC, and PRXCLAV will be
sampled at the end of the next clock cycle. If no secondary SAR is used, ground
this pin at the MT90500 and PHY devices. Note that the UTOPIA standard permits
this signal to be permanently asserted (see UTOPIA Level 1, V2.01, footnote 6).
Primary UTOPIA receive cell available indication signal. For cell level flow control,
PRXCLAV is asserted by the PHY to indicate it has a complete cell available for
transfer to the RX UTOPIA port.
Primary UTOPIA bus receive clock. This clock, which can run at up to 25 MHz, is
provided by the secondary SAR device. If no secondary SAR is used, connect to
PTXCLK (this will provide exact compliance with the UTOPIA Level 1, V2.01
specification).
Description
MT90500
19