MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 106

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

MT90500
106
Address: 6090 (Hex)
Label: MCGCR
Reset Value: 00C0 (Hex)
DIVCLK_SRC
EX_8KA_SQ
SEC8K_SQ
SEC8KSEL
SEC8KEN
REFSEL
DIV1...8
PHLEN
BEPLL
Label
Bit Position
1:0
7:6
10
2
3
4
5
8
9
Table 61 - Master Clock Generation Control Register
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
REF8KCLK (8 kHz Reference Clock) Selection. See Figure 3 on page 29.
00 -> MCLK/(DIVCLK + 2) or CLKx2/(DIVCLK + 2) (See register 6092h.)
01 -> RXVCLK (recovered ATM VC/SW clock. See register 60A8h.)
10 -> SEC8K input pin
11 -> EX_8KA input pin.
Selects input clock for programmable divider (See register 6092h.)
0 -> MCLK
1 -> CLKx2
Select squared version of EX_8KA for output.
0 -> Pass EX_8KA signal without changes,
1 -> Convert EX_8KA input to square wave.
This bit, when HIGH, selects the squared version of EX_8KA for routing to the
REF8KCLK, and the SEK8K multiplexers. The squaring logic converts the EX_8KA input
into a square wave (approximately 50% duty-cycle). This can convert a pulse 8 kHz signal
into an 8 kHz square wave, for example. The rising edge of EX_8KA input is passed,
without added jitter, to the REF8KCLK or SEC8K output as a falling edge (i.e. the signal is
inverted); the rising edge at the REF8KCLK output will be 50% duty cycle with jitter equal
to a cycle of MCLK. MCLK must be at least 10 times faster, and at most 16000 times
faster, than EX_8KA. See Figure 3, “TDM Clock Selection and Generation Logic,” on
page 29.
Enable SEC8K squaring logic.
0 -> Pass SEC8K signal without changes,
1 -> Convert SEC8K input to square wave.
The squaring logic, when enabled, converts the SEC8K input into a square wave
(approximately 50% duty-cycle) before passing it to the REF8KCLK multiplexer. This can
convert a pulse 8 kHz signal into an 8 kHz square wave, for example. When REFSEL =
“10” the rising edge of SEC8K input is passed, without added jitter, to the REF8KCLK
output as a rising edge; the falling edge at the REF8KCLK output will be 50% duty cycle
with jitter equal to a cycle of MCLK. MCLK must be at least 10 times faster, and at most
16000 times faster, than SEC8K.
Clock Generator Multiplexer Selection: selects CLK16 input clock for the TDM Clock
Generator.
0 -> MCLK
1 -> PLLCLK input.
Clock Generator Division Factor. (“11” at reset)
00 -> 8
01 -> 1
10 -> 2
11 -> 4
Note: These bits provide the factor by which either MCLK or PLLCLK (as determined by
BEPLL) is divided to provide a 16.384 MHz clock at the Main TDM Bus Clock Generation
Logic .
Clock Generator Phase Lock Enable. When this bit is ‘1’, and TDMFS (in the TDM Bus
Type Register at 6010h) is “00”, the internal FSYNC signal generator will be slaved to the
external FSYNC signal.
This bit allows the MT90500 to be used as a Clock Master Alternate in SCSA mode (i.e.
CLKALT = ‘1’ and CLKMASTER = ‘0’ in TDM Bus Type Register at 6010h). In this case,
the stand-by clock master circuit (using CLK16, the local 16.384 MHz clock derived from
PLLCLK or MCLK) tracks the external FSYNC signal so that when it is selected as a clock
master after a clock failure, the new FSYNC will be almost in phase with the previous one.
The phase-tracking is automatically disabled when the CLKFAIL input pin is
asserted.
When ‘1’, the MT90500 drives the SEC8K external signal. When ‘0’, the SEC8K pin is an
input.
SEC8K Clock Source Selection
0 -> EX_8KA
1 -> Internally generated 8 kHz reference (FS_INT)
Description