MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 125

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

Address Setup - (AEM and A[15:1]
VALID) to (CS and WR asserted)
Address Hold - (CS or WR de-
asserted)
INVALID)
RDY De-asserted - (CS and WR
asserted) to RDY de-asserted
RDY Delay - (CS and WR asserted) to
RDY asserted
Write Cycle Hold Time - RDY asserted
to (CS or WR de-asserted)
Data Input Setup - D[15:0] VALID to
(CS and WR asserted)
Data Input Hold - (CS or WR de-
asserted) to D[15:0] INVALID
Note 1: MCLK = 60 MHz (16.6 ns).
Note 2: Both CS and WR must be asserted for a write cycle to occur. A write cycle is completed when either CS or WR is de-asserted.
Note 3: There should be a minimum of 4 MCLK periods between CPU accesses, to allow the MT90500 to recognize the accesses as
separate.
D[15:0]
WR
CS
RD
A[15:1]
AEM
RDY
Characteristic
to
t
(AEM
ADDS
t
DS
Table 85 - Intel Microprocessor Interface Timing - Write Cycle Parameters
t
RDY
and
A[15:1]
Figure 52 - Intel CPU Interface Timing - Write Access
t
t
t
t
Sym
ADDS
ADDH
t
RDYD
WRH
RDY
t
t
DS
DH
Min
100
0
0
0
0
0
ADDRESS VALID
DATA VALID
t
RDYD
Typ
415
1000
Max
21
Units
ns
ns
ns
ns
ns
ns
ns
1) ~ 1 MCLK cycle + 4 ns
2) C
1) 6 MCLK < t
2) C
t
WRH
L
L
= 50 pF
= 50 pF
Test Conditions
t
ADDH
t
RDYD
DH
MT90500
< 60 MCLK
V
V
V
V
V
V
TT
TT
TT
TT
TT
TT
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