MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 74

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

MT90500
4.6.2.2
Note: The following specification assumes that the MT90500 will perform the SRTS function with the use of
external logic as depicted in Figure 35 and Figure 36.
On the receive side, the MT90500 will generate a local RTS value (EXPECTED_SRTS) as depicted in
Figure 34 (and in a manner identical to that explained in detail in Section 4.6.2.1 for the transmit direction), and
will compare it with the received RTS code (RX_SRTS) from the incoming ATM stream. Up to five locally-
generated RTS values can be stored in a series of internal latches (a 5-deep FIFO).
The MT90500 internal comparator generates a 4-bit complement code that indicates the difference between
the locally generated RTS value and the incoming RTS value (remote - local). The value of this code ranges
from -8 (1000) to +7 (0111). The result of the comparison is then sent out via the SRTSDATA pin, with an
associated strobe output transmitted on SRTSENA. External user logic is necessary to monitor these
difference values, perform the clock adjustment and recover the original ST-BUS clock. If the difference values
increase, it is due to the fact that the remote bus is running faster than the local bus and therefore the local bus
frequency must be increased. Likewise, if the difference values are decreasing, it is because the remote bus is
running more slowly than the local bus, and thus the local bus must be slowed down.
Two 5-deep FIFOs are used to minimize the effect of cell delay variation in the transmission and reception
process and to minimize slips. For both the receive SRTS and the transmit SRTS processes, the FIFOs are
self-aligning: if an underrun or overrun is encountered, the FIFOs’ pointers are re-centered. These errors are
reported in the Clock Module General Status Register at 6082h.
74
Receive
ATM Cells
w/ CSI b
CLKx1
ATM Physical Layer
Network Clock
its
Receive SRTS Operation
Gapping Control
f
B
SRTS Receive Divider Register
Generator
f
B
= f
S
/ 8 = service byte clock
f
B
Divide by x
Byte Counter
Figure 34 - Receive SRTS Operation
FNXI
period of the RTS
(one 8-cell cycle)
f
RX_SAR
nx
BLOCK
clk
4-bit counter
data_in
RX_SRTS
MULTIPLE
LATCHES
enable
Internal to MT90500
4
4
Comparator
EXPECTED_
SRTS
enable
4
SRTSENA
SRTSDATA