MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 110

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

MT90500
110
Address: 60B2(Hex)
Label: SRTBC
Reset Value: 0177 (Hex)
Address: 60B4(Hex)
Label: SRRGD
Reset Value: 0000 (Hex)
Address: 60B6(Hex)
Label: SRRBC
Reset Value: 0177 (Hex)
RX_Ch_per_VC
Byte Number
Byte Number
RX_Gapping
Reserved
Reserved
Reserved
Label
Label
Label
Bit Position
Bit Position
Bit Position
15:9
14:8
15:9
8:0
7:0
8:0
15
Table 71 - SRTS Receive Gapping Divider Register
Table 70 - SRTS Transmit Byte Counter Register
Table 72 - SRTS Receive Byte Counter Register
Type
Type
Type
R/W
R/W
R/W
R/W
R/W
R/O
R/O
Number of TDM payload bytes in eight (8) consecutive cells. For pointerless AAL1
Structured Data Transfer (i.e. n=1 SDT), this value is 376. For AAL1 SDT (n not equal to
1), this value is normally 375 (although it may be 374, or 372, depending on the number of
P-bytes sent in each 8-cell sequence).
Always read “0000_000”
This field provides the separation between consecutive pulses of the f
should be set according to the following formula: (256 / number of channels per VC) - 1.
The result must be rounded down.
1 channel -> 255
2 channels -> 127
3 channels -> 84
...
Number of channels in the VC that is selected for receiving the SRTS.
0 -> 1 channel
1 -> 2 channels
...
Note: Since maximum number of channels per VC is 122, values 7A:7F are reserved.
Reserved. Should be written as ‘0’.
Number of TDM payload bytes in eight (8) consecutive cells. For pointerless AAL1-
Structured Data Transfer (i.e. n=1 SDT), this value is 376. For AAL1 SDT (n not equal to
1), this value is normally 375 (although it may be 374, or 372, depending on the number of
P-bytes sent in each 8-cell sequence).
Always read “0000_000”
Description
Description
Description
B
clock. This field