MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 21

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

Note: MT90500 3.3 V CMOS inputs are pulled up to the 3.3 Volt rail. See Table 76 on page 112.
178, 179, 149,
123, 122, 121,
118, 117, 116,
115, 103, 102,
130, 128, 127,
166, 167, 168,
170, 171, 173,
174, 175, 153,
154, 155, 156,
158, 159, 162,
164, 133, 134,
135, 136, 137,
138, 142, 143,
105, 106, 107,
108, 109, 112,
165, 152, 131,
126, 125, 124
99, 146, 144,
113, 114
Pin #
147
176
148
177
150
180
104
98
MEM_ADD[17:0]
MEM_DAT[31:0]
MEM_PAR[3:0]
MEM_WR[3:0]
MEM_CS0H
MEM_CS1H
MEM_CS0L
MEM_CS1L
Pin Name
MEMCLK
MEM_OE
I/O
I/O
I/O
O
O
O
O
O
O
O
O
Table 4 - External Memory Interface Pins
PU / 3.3V 4mA
PU / 3.3V 4mA
3.3V CMOS
3.3V CMOS
3.3V, 4mA
3.3V, 4mA
3.3V, 4mA
3.3V, 4mA
3.3V, 4mA
3.3V, 4mA
3.3V, 4mA
3.3V, 4mA
Type
Memory Clock. Internally connected to MCLK.
Active LOW memory chip select signal. This chip select is used in all memory
modes. When there are two chips per bank, MEM_CS0L is associated with
MEM_DAT[15:0] of Bank 0.
Active LOW memory chip select signal. This chip select is used when there
are two 16-bit memory chips per bank. MEM_CS0H is associated with
MEM_DAT[31:16] of Bank 0.
Active LOW memory chip select signal. This chip select is used when there
are two banks and two chips per bank. MEM_CS1L is associated with
MEM_DAT[15:0] of Bank 1.
Active LOW memory chip select signal. This chip select is used when there
are two banks and two chips per bank. MEM_CS1H is associated with
MEM_DAT[31:16] of Bank 1.
Active
MEM_DAT[31:24]; MEM_WR[2] is associated with MEM_DAT[23:16];
MEM_WR[1] is associated with MEM_DAT[15:8]; MEM_WR[0] is associated
with MEM_DAT[7:0].
Active LOW output enable.
Memory address lines.
Memory
MEM_DAT[23:16]
represent the lower-middle byte; MEM_DAT[7:0] represent the lower byte.
Memory parity lines. MEM_PAR[3:0] are the optional “parity” bits that allow
TDM Read Underrun detection. MEM_PAR[3] is related to MEM_DAT[31:24],
MEM_PAR[2] is related to MEM_DAT[23:16], MEM_PAR[1] is related to
MEM_DAT[15:8], and MEM_PAR[0] is related to MEM_DAT[7:0]. When
unused, these pins must be pulled up via external resistors.
LOW
data
byte-write
lines.
represent
MEM_DAT[31:24]
enables.
the
Description
upper-middle
MEM_WR[3]
represent
byte;
is
MT90500
the
associated
MEM_DAT[15:8]
upper
byte;
with
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