MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 126

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

MT90500
126
Address Setup - (R/W, AEM and
A[15:1]
asserted)
Address Hold - (CS or DS de-
asserted) to (AEM, A[15:1] and R/W
INVALID)
DTACK High - (CS and DS asserted) to
DTACK driving one
DTACK Delay - (CS and DS asserted)
to DTACK asserted
Data to DTACK Delay - D[15:0] VALID
to DTACK asserted
DTACK Hold - (CS or DS de-asserted)
to DTACK driving high
DTACK High-Impedance - (CS or DS
de-asserted)
impedance
Data Output Hold - (CS or DS de-
asserted) to D[15:0] INVALID
Note 1: MCLK = 60 MHz (16.6 ns).
Note 2: Both CS and DS must be asserted for a read cycle to occur. A read cycle is completed when either CS or DS is de-asserted.
Note 3: There should be a minimum of 4 MCLK periods between CPU accesses, to allow the MT90500 to recognize the accesses as
separate.
DS
CS
DTACK
A[15:1]
AEM
R/W
D[15:0]
VALID)
Characteristic
t
ADDS
to
Table 86 - Motorola Microprocessor Interface Timing - Read Cycle Parameters
to
DTACK
(CS
and
t
DTK1
high-
Figure 53 - Motorola CPU Interface Timing - Read Access
DS
t
t
t
t
t
t
t
Sym
ADDS
ADDH
DTKD
DDTK
DTKH
DTKZ
DTK1
t
DH
t
DTKD
Min
100
14
ADDRESS VALID
0
0
5
6
3
Typ
375
1000
Max
34
15
20
15
t
DDTK
Units
ns
ns
ns
ns
ns
ns
ns
ns
DATA VALID
t
t
ADDH
ADDH
1) ~ 2 MCLK cycles
2) C
1) 6 MCLK < t
2) C
1) ~ 1 MCLK cycle - 2 ns
2) C
C
C
1) Min. measurement is to D[15:0]
INVALID; max. measurement is to
D[15:0] high-impedance
2) C
t
DTKH
L
L
= 50 pF
= 50 pF
L
L
L
L
= 50 pF
= 50 pF
= 50 pF
= 50 pF
Test Conditions
RDYD
t
DH
< 60 MCLK
t
DTKZ
V
V
V
V
V
V
TT
TT
TT
TT
TT
TT