MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 82

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

MT90500
5.1.3
82
Microprocessor Interface Registers
TX_SAR Registers
RX_SAR Registers
UTOPIA Registers
Address
0000
0002
0010
0012
0030
0032
0034
0036
0040
2000
2002
2010
2012
2014
2020
2022
2024
2030
2032
2034
2040
2050
2052
2054
3000
3002
3010
3012
3020
3022
3030
3032
4000
4002
4010
4012
4014
4016
4018
401A
Hex
Register Summary
MEMCNF
Reserved
Reserved
Reserved
Reserved
TXDFWP
RXMECT
TESERC
RXUECT
RXOECT
TESBAA
TESFEA
TESERA
TESBAB
TESFEB
TESERB
TESBAC
TESFEC
TXCSBA
TXDFBA
TXDFRP
WTEMC
RXMEID
RXUEID
RXOEID
RDPAR
RXSCR
RXSSR
VPVCC
VPITIM
VPMS
VCMT
VCMS
TXSC
VPMT
Label
TXSS
MCR
MSR
UCR
USR
Reset
Value
0000
00X0
0000
0001
0000
0000
0000
0000
0008
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
Main Control Register
Main Status Register
Reserved - DO NOT WRITE
Reserved - DO NOT WRITE
Window to External Memory Register - CPU
Reserved - DO NOT WRITE
Reserved - DO NOT WRITE
Read Parity Register
Memory Configuration Register
TX_SAR Control Register
TX_SAR Status Register
TX_SAR Scheduler Base Register - Scheduler A
TX_SAR Frame End Register - Scheduler A
TX_SAR End Ratio Register - Scheduler A
TX_SAR Scheduler Base Register - Scheduler B
TX_SAR Frame End Register - Scheduler B
TX_SAR End Ratio Register - Scheduler B
TX_SAR Scheduler Base Register - Scheduler C
TX_SAR Frame End Register - Scheduler C
TX_SAR End Ratio Register - Scheduler C
TX_SAR Control Structure Base Address Register
Transmit Data Cell FIFO Base Address Register
Transmit Data Cell FIFO Write Pointer Register
Transmit Data Cell FIFO Read Pointer Register
RX_SAR Control Register
RX_SAR Status Register
RX_SAR Misc. Event ID Register
RX_SAR Misc. Event Counter Register
RX_SAR Underrun Event ID Register
RX_SAR Underrun Event Counter Register
RX_SAR Overrun Event ID Register
RX_SAR Overrun Event Counter Register
UTOPIA Control Register
UTOPIA Status Register
VPI / VCI Concatenation Register
VPI Match Register
VPI Mask Register
VCI Match Register
VCI Mask Register
VPI Timing Register
Table 11 - Register Summary
Description