MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 87

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

5.2.2
Address: 2002 (Hex)
Label: TXSS
Reset Value: 0000 (Hex)
Address: 2000 (Hex)
Label: TXSC
Reset Value: 0000 (Hex)
SCHEDULE_IE
AUTODATA
TXFFORIE
TXFFENA
TXFFRP+
Reserved
SCENA
SAENA
SBENA
TESTS
Reserved
TXFFOR
Label
Label
TX_SAR Registers
Bit Position
15:9
Position
0
1
2
3
4
5
6
7
8
4:0
Bit
5
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/O
R/O/L
Type
R/O
Table 17 - TX_SAR Control Register
Table 18 - TX_SAR Status Register
Scheduler A Enable. ‘0’ = Disabled; ‘1’ = Enabled. Before enabling this scheduler, all its
configuration registers must be written and valid. These registers must not be changed
while SAENA is HIGH. If an event scheduler is re-configured (i.e. changes made to 2010h,
2012h, or 2014h), all of its events and dependent structures should be re-initialized before
starting the scheduler again.
Scheduler B Enable. ‘0’ = Disabled; ‘1’ = Enabled. Before enabling this scheduler, all its
configuration registers must be written and valid. These registers must not be changed
while SBENA is HIGH. If an event scheduler is re-configured (i.e. changes made to 2020h,
2022h, or 2024h), all of its events and dependent structures should be re-initialized before
starting the scheduler again.
Scheduler C Enable. ‘0’ = Disabled; ‘1’ = Enabled. Before enabling this scheduler, all its
configuration registers must be written and valid. These registers must not be changed
while SCENA is HIGH. If an event scheduler is re-configured (i.e. changes made to 2030h,
2032h, or 2034h), all of its events and dependent structures should be re-initialized before
starting the scheduler again.
Transmit FIFO Enable. When this bit is LOW, the Transmit Data Cell FIFO Read Pointer
(TXFFRP in TXDFRP at 2054h) is reset to 00h. When this bit is HIGH, the FIFO can
operate normally.
When this bit is ‘1’, non-CBR data cells (the next cells located in the Transmit Data Cell
FIFO) will be transmitted while the TX_SAR is idle. When this bit is ‘0’, data cell
transmission is controlled by the schedulers.
Transmit Data Cell FIFO Overrun Error Interrupt Enable. ‘0’ = Disabled; ‘1’ = Enabled.
When enabled, a ‘1’ on TXFFOR in Register 2002h will force a ‘1’ on TX_SAR_SERV in
Register 0002h.
Scheduler Error Interrupt Enable. ‘0’ = Disabled; ‘1’ = Enabled. When enabled, a ‘1’ on
SCHEDULE in Register 2002h will force a ‘1’ on TX_SAR_SERV in Register 0002h.
Increment Transmit Data Cell FIFO Read Pointer. When ‘1’ is written to this bit, the
Transmit Data Cell FIFO Read Pointer (TXFFRP) is incremented. Used for test purposes
only.
Test Status. When HIGH, this bit forces all the status events in TX_SAR Status Register at
2002h to occur. Used for test purposes only.
Reserved. Always read as “0000_000”.
Reserved. Always read as “0_0000”.
Transmit Data FIFO Overrun. When set, this bit indicates that the CPU changed the value
of the Transmit Data Cell FIFO Write Pointer (2052h) to the value of the Transmit Data Cell
FIFO Read Pointer (2054h). When this event occurs, the MT90500 assumes that the CPU
is trying to write one more non-CBR cell than the FIFO can contain. Writing a ‘1’ over this
bit clears it.
Description
Description
MT90500
87