MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 117

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

Clock Skew - CLKx2 falling to CLKx1 change
CLKx2 - Input Clock Period
CLKx2 Input Pulse Width (HIGH / LOW)
CLKx1 - Input Clock Period
CLKx1 Pulse Width (HIGH / LOW)
PLLCLK - Input Clock Period
PLLCLK Pulse Width (HIGH / LOW)
Frame Pulse Setup Time
FSYNC valid to CLKx2 falling (TCLKSYN = 1)
FSYNC valid to CLKx1 rising (negative FSYNC)
FSYNC valid to CLKx1 falling (positive FSYNC)
Frame Pulse Hold Time
CLKx2 falling to FSYNC invalid (TCLKSYN = 1)
CLKx1 rising to FSYNC invalid (negative FSYNC)
CLKx1 falling to FSYNC invalid (positive FSYNC)
STi Setup Time - STi VALID to CLKx1 falling
STi Hold Time - CLKx1 falling to STi INVALID
STi Setup Time - STi VALID to CLKx2 rising
STi Hold Time - CLKx2 rising to STi INVALID
STi Setup Time - STi VALID to CLKx1 rising
STi Hold Time - CLKx1 rising to STi INVALID
2.048 Mbps bus (4.096 MHz clock)
4.096 Mbps bus (8.192 MHz clock)
8.192 Mbps bus (16.384 MHz clock)
2.048 Mbps bus (4.096 MHz clock)
4.096 Mbps bus (8.192 MHz clock)
8.192 Mbps bus (16.384 MHz clock)
2.048 Mbps
4.096 Mbps
8.192 Mbps
2.048 Mbps
4.096 Mbps
8.192 Mbps
16.384 MHz
16.384 MHz
2/4 Sampling
2/4 Sampling
3/4 Sampling
3/4 Sampling
4/4 Sampling
4/4 Sampling
Characteristic
Characteristic
Table 79 - Main TDM Bus Input Clock Parameters
Table 80 - Main TDM Bus Input Data Parameters
t
t
t
Cx2H/L
Cx1H/L
PLLH/L
t
t
Sym
Sym
t
Cx2P
Cx1P
t
t
t
t
t
t
t
t
t
FSK
PLL
FIS
FIH
SIS
SIH
SIS
SIH
SIS
SIH
195.2
97.6
48.8
26.2
97.6
48.8
26.2
Min
10
10
10
Min
5
5
5
10
10
10
5
5
5
30.5
30.5
Typ
244
122
122
488
244
122
244
122
61
61
61
61
Typ
146.4
292.8
146.4
Max
73.2
34.8
73.2
34.8
10
Max
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
16.39 MHz (61 ns) input clock
with 50/50 duty cycle
16.39 MHz (61 ns) input
clock
MT90500 is TDM Timing Bus
Slave.
MT90500 is TDM Timing Bus
Slave.
.
Test Conditions
Test Conditions
MT90500
.
117