MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 71

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

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The RXVCLK Clock Generation Block is composed of:
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Together, the Adaptive Clock Recovery Block and the RXVCLK Clock Generation Block allow the CPU to
implement an adaptive algorithm which permits the locally generated TDM clock to track the remotely
generated TDM clock.
the Event Counter, which keeps a running count of the timing reference cells or 8 kHz markers received.
The Cell/8 kHz bit in the Timing Reference Processing Control Register (address 60A0h) is used to
select whether clock recovery is based on Timing Reference Cell arrival events, or 8 kHz marker events.
The Event Count Register (60A2h) is updated every time the CNTUPDATE bit is set HIGH in the Clock
Module General Control Register at 6080h.
a counter which is incremented every eight cycles of CLKx1. The output of this counter is sent to the
Temp Register, which is updated every time the Event Counter is incremented. Finally, the CLKx1 Count
Registers (60A4h and 60A6h) are updated every time the CNTUPDATE bit is set HIGH in the Clock
Module General Control Register at 6080h.
a programmable divider (DIVX Register at address 60A8h) which divides the master IC clock (MCLK) in
order to obtain RXVCLK.
a division factor register (DIVX Ratio Register at address 60AAh) which controls the ratio of divide-by-X
to divide-by-(X+1).
any consecutive error
BAD_SNP
- When going to In_Sync or Bad SNP state, generate one timing reference pulse for each timing
cell received. (“Bad SNP” is bad Sequence Number Protection, meaning a bad CRC, or a bad par-
ity bit.)
- When going to Lost Cell state, generate two timing reference pulses.
- When coming back to In_Sync state from Lost Cell state, generate one pulse if “next sequence”
received. Do not generate pulse if “previous sequence” received, indicating an inverse-ordered
cell condition.
- When in Out_of_Sync state, do not generate timing pulses. If OUT_SYNC_IE bit is set at 6080h,
and TIM_INTE is set at 0000h, an interrupt will be generated on entering Out_Of_Sync.
- If no timing reference cells or markers have been received within the time-out period set in the
Timing Reference Processing Control Register (60A0h), a Loss of Timing Reference Cells event
will be indicated (LOSS_TIMRF in 6082h), and an interrupt will be generated if LOSSCIE is set at
6080h (and TIM_INTE is set at 0000h).
Figure 32 - Timing Reference Cell Processing State Machine
next sequence
(good SNP)
Bad SNP
(except 2nd next)
out of sequence
next sequence
OUT_OF_
IN_SYNC
SYNC
next sequence
2nd next sequence
previous sequence
next sequence
out of sync (any consecutive
LOST_CELL
MT90500
error)
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