IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 93

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

External Microprocessor Registers
Microprocessor Indirect Access Control Register
Microprocessor Indirect Access Data Register - 1
ERROR
RWN
BUSY
DATA[0:7]
IDT IDT88K8483
Field
Field
1
2
3
4
5
6
7
8
9 to 0x3C
0x3D
0x3E
0x3F
R
R/W
R
R/W
Read /
Read /
Write
Write
Error Code
Table 27 Microprocessor Indirect Access Control Register
Table 29 Microprocessor Indirect Access Data Register -1
0:0 - 0:5
0:0 - 0:7
0:6
0:7
Bits
Bits
Reconfiguration attempted without device reset, configuration is allowed only once after
reset for this register
Multiple LPs mapped to the same LID
Multiple LIDs mapped to the same LP
Buffer segment assigned exceeds total available segments
Buffer segment assigned exceeds total number of queue entries available
Configuration modified while link active
Undefined address
Channel limit exceeded
Reserved
Version mismatch
Protected register
Internal timeout
6
1
1
8
Length
Length
Table 28 Microprocessor Indirect Access Error Codes
0
0
0
0
Reset
Reset
State
State
93 of 162
Indicates the error code of a READ or WRITE operation.
0: No error.Operation performed successfully
Error code- see Table 28 below for description of error codes.
Indicates the initiation of a read or write operation by the OBC.
0: A write operation is initiated by the OBC.
1: A read operation is initiated by the OBC.
Gives a busy indication if an indirect READ or WRITE is initiated. The flag is set until
the operation is completed.
0: Not busy.
1: Busy indication.
This register contains the first byte of the 4 byte data that is to be written to or read
from the indirect register.
Error
(Register Offset=0x1B)
(Register Offset=0x1A)
Description
Description
October 20, 2006