IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 7

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

IDT IDT88K8483
Table 108. PFP Ingress Status Monitor Register - 3 (Block Base=0x1700/0x1F00, Register Offset=0x07) . . . . . . . . . . . . . . . .126
Table 109. PFP Ingress Status Monitor Register - 4 (Block Base=0x1700/0x1F00, Register Offset=0x08) . . . . . . . . . . . . . . . .126
Table 110. PFP Egress Status Monitor Register - 1 (Block Base=0x1700/0x1F00, Register Offset=0x09) . . . . . . . . . . . . . . . .127
Table 111. PFP Egress Status Monitor Register - 2 (Block Base=0x1700/0x1F00, Register Offset=0x0A) . . . . . . . . . . . . . . . .127
Table 112. PFP Egress Status Monitor Register - 3 (Block Base=0x1700/0x1F00, Register Offset=0x0B) . . . . . . . . . . . . . . . .127
Table 113. PFP Egress Status Monitor Register - 4 (Block Base=0x1700/0x1F00, Register Offset=0x0C) . . . . . . . . . . . . . . . .127
Table 114. PFP Internal Parity Error Indication Register (Block Base=0x1700/0x1F00, Register Offset=0x0D) . . . . . . . . . . . .127
Table 115. PFP Maximum Packet Length Register (Block Base=0x1700/0x1F00, Register Offset=0x0E) . . . . . . . . . . . . . . . .128
Table 116. Auxiliary Interface Enable Register (Block Base=0x0A00, Register Offset=0x00) . . . . . . . . . . . . . . . . . . . . . . . . . .129
Table 117. Auxiliary Interface Configuration Register (Block Base=0x0A00, Register Offset=0x01) . . . . . . . . . . . . . . . . . . . . .129
Table 118. Auxiliary Extension Buffer Configuration Register (Block Base=0x0A00, Register Offset=0x02) . . . . . . . . . . . . . . .129
Table 120. Auxiliary Clock Monitor Status Register (Block Base=0x0A00, Register Offset=0x03) . . . . . . . . . . . . . . . . . . . . . . .130
Table 121. External Memory Test Control Register (Block Base=0x0A00, Register Offset=0x04) . . . . . . . . . . . . . . . . . . . . . . .130
Table 119. External Memory Segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
Table 122. External Memory Test Results Register (Block Base=0x0A00, Register Offset=0x05) . . . . . . . . . . . . . . . . . . . . . .131
Table 123. Auxiliary Early Backpressure Threshold Register (Block Base=0x0A00, Register Offset=0x07) . . . . . . . . . . . . . . .131
Table 124. Auxiliary Packet Mode Configuration Register (Block Base=0x0A00, Register Offset=0x08) . . . . . . . . . . . . . . . . .131
Table 125. Auxiliary HSTL Receiver Test Control Register (Block Base=0x0A00, Register Offset=0x0E) . . . . . . . . . . . . . . . .131
Table 126. Auxiliary Automatic Impedance Matching Control Register (Block Base=0x0A00, Register Offset=0x0F) . . . . . . . .132
Table 127. Auxiliary Synchronization Status Register (Block Base=0x0A00, Register Offset=0x12) . . . . . . . . . . . . . . . . . . . . .132
Table 128. Auxiliary Initialization Control Register (Block Base=0x0A00, Register Offset=0x013) . . . . . . . . . . . . . . . . . . . . . .133
Table 129. Enable Control Register (Block Base=0x0B00, Register Offset=0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Table 130. Feedback Configuration Register (Block Base=0x0B00, Register Offset=0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Table 131. Bandwidth Control Register (Block Base=0x0B00, Register Offset=0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Table 132. Bandwidth level as per field BW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Table 133. Packet Length Register (Block Base=0x0B00, Register Offset=0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Table 134. Burst Size Register (Block Base=0x0B00, Register Offset=0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Table 135. Random Control Register (Block Base=0x0B00, Register Offset=0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Table 136. LID Register (Block Base=0x0B00, Register Offset=0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
Table 137. Synchronization Register (Block Base=0x0B00, Register Offset=0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
Table 138. Bit Error Insertion Register (Block Base=0x0B00, Register Offset=0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
Table 139. PMON Event Interrupt Indication Register (Block Base=0x0F00, Register Offset=0x00) . . . . . . . . . . . . . . . . . . . . .136
Table 140. PMON Event Interrupt Enable Register (Block Base=0x0F00, Register Offset=0x01) . . . . . . . . . . . . . . . . . . . . . . .139
Table 141. PMON Buffer T-M Overflow Indication Register (Block Base=0x0F00, Register Offset=0x02-0x03) . . . . . . . . . . . .140
Table 142. PMON Buffer M-T Overflow Indication Register (Block Base=0x0F00, Register Offset=0x04-0x05) . . . . . . . . . . . .141
Table 143. PMON Buffer T-M Overflow Interrupt Control Register (Block Base=0x0F00, Register Offset=0x06-0x07) . . . . . . .141
Table 144. PMON Buffer M-T Overflow Interrupt Control Register (Block Base=0x0F00, Register Offset=0x08-0x09) . . . . . . .141
Table 145. PMON Buffer Overflow Source Register (Block Base=0x0F00, Register Offset=0x0A) . . . . . . . . . . . . . . . . . . . . . .142
Table 146. PMON T-M Inactive Transfer LP Field Register (Block Base=0x0F00, Register Offset=0x0B) . . . . . . . . . . . . . . . .142
Table 147. PMON M-T Inactive Transfer LP Field Register (Block Base=0x0F00, Register Offset=0x0C) . . . . . . . . . . . . . . . .142
Table 148. PMON T-M Illegal SOP Event Field Register (Block Base=0x0F00, Register Offset=0x0D) . . . . . . . . . . . . . . . . . .142
Table 149. PMON T-M Illegal EOP Event Field Register (Block Base=0x0F00, Register Offset=0x0E) . . . . . . . . . . . . . . . . . .142
Table 150. PMON M-T Illegal SOP Event Field Register (Block Base=0x0F00, Register Offset=0x0F) . . . . . . . . . . . . . . . . . .143
Table 151. PMON M-T Illegal EOP Event Field Register (Block Base=0x0F00, Register Offset=0x10) . . . . . . . . . . . . . . . . . .143
Table 152. PMON T-M Packet Cut-Down LID Field Register (Block Base=0x0F00, Register Offset=0x11) . . . . . . . . . . . . . . .143
Table 153. PMON M-T Packet Cut-Down LID Field Register (Block Base=0x0F00, Register Offset=0x12) . . . . . . . . . . . . . . .143
Table 154. PMON Per LID Counter Table (Block Base=0x0C00, Register Offset=0x00-0x17F) . . . . . . . . . . . . . . . . . . . . . . . .144
Table 155. PMON Per Module/Interface Counter Table (Block Base=0x0E00 Register Offset=0x00-0x10 . . . . . . . . . . . . . . . .144
Table 156. PMON Timebase Control Register (Block Base=0x8B00, Register Offset=0x00) . . . . . . . . . . . . . . . . . . . . . . . . . .145
Table 157. Timebase source table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
Table 158. PMON 1ms Timer Register (Block Base=0x8B00, Register Offset=0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
Table 159. GPIO Direction Register (Block Base=0x8B00, Register Offset=0x10-0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
Table 160. GPIO Level Register (Block Base=0x8B00, Register Offset=0x13-0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
Table 161. GPIO Link Table (Block Base=0x8B00, Register Offset=0x16-0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
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October 20, 2006