IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 6

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

Table 54. SPI-4 Ingress LP to LID Mapping Table (Block Base=0x0000, Register Offset=0x00-0xff) . . . . . . . . . . . . . . . . . . .105
Table 55. SPI-4 Ingress Calendar 0 Table (Block Base=0x0100, Register Offset=0x00-0x3f/0x7f) . . . . . . . . . . . . . . . . . . . . .105
Table 56. Ingress Calendar 1 Table (Block Base=0x0200, Register Offset=0x00-0x3f/0x7f) . . . . . . . . . . . . . . . . . . . . . . . . . .105
Table 57. SPI-4 Interface Enable Register (Block Base= 0x0300, Register Offset=0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Table 58.
Table 59. SPI-4 Ingress Training Parameter Register (Block base=0x0300, Register Offset=0x02) . . . . . . . . . . . . . . . . . . . .107
Table 60. SPI-4 Ingress Calendar 0 Configuration Register (Block Base=0x0300, Register Offset=0x03) . . . . . . . . . . . . . . .107
Table 61. SPI-4 Ingress Calendar 1 Configuration Register (Block base=0x0300, Register Offset=0x04) . . . . . . . . . . . . . . .108
Table 62. SPI-4 Ingress Status Register (Block base=0x0300, Register Offset=0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Table 63. SPI-4 Ingress Diagnostics Register (Block base=0x0300, Register Offset=0x06) . . . . . . . . . . . . . . . . . . . . . . . . . .109
Table 64. SPI-4 Ingress Automatic Alignment Control Register (Block base=0x0300, Register Offset=0x07) . . . . . . . . . . . . .109
Table 65. SPI-4 Ingress Calendar Switch Control Register (Block base=0x0300, Register Offset=0x08) . . . . . . . . . . . . . . . .109
Table 66.
Table 67. Ingress calendar Switch Register: Bit I_DIP_CSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Table 68. SPI-4 Ingress Fill Level Register (Block base=0x0300, Register offset=0x0B-0x0C) . . . . . . . . . . . . . . . . . . . . . . . .110
Table 69. SPI-4 Ingress Max Fill Level Register (Block Base=0x0300, Register Offset=0x0D-0x0E . . . . . . . . . . . . . . . . . . . .110
Table 70. SPI-4 Ingress Watermark Register (Block Base=0x0300, Register Offset=0x0F-0x10) . . . . . . . . . . . . . . . . . . . . . .111
Table 71. Ingress Training to out of sync threshold Registe(Block Base=0x0300,Register Offset=0x13) . . . . . . . . . . . . . . . .111
Table 72. SPI-4 Egress LID To LP Mapping Table (Block Base=0x0400, Register Offset=0x00-0x3F/0x7F) . . . . . . . . . . . . .111
Table 73. SPI-4 Egress Calendar 0 Table (Block Base=0x0500, Register Offset=0x00-0x3F/0x7F) . . . . . . . . . . . . . . . . . . . .111
Table 74. SPI-4 Egress Calendar 1 Table (Block Base=0x0600, Register Offset=0x00-0x3F/0x7F) . . . . . . . . . . . . . . . . . . . .112
Table 75. SPI-4 Egress Configuration Register (Block Base=0x0800, Register Offset=0x01) . . . . . . . . . . . . . . . . . . . . . . . . .113
Table 76. SPI-4 Egress Training Parameter Register (Block Base=0x0800, Register Offset=0x02) . . . . . . . . . . . . . . . . . . . .113
Table 77. SPI-4 Egress Calendar 0 Configuration Register (Block Base=0x0800, Register Offset=0x03) . . . . . . . . . . . . . . . .114
Table 78. SPI-4 Egress Calendar 1 Configuration Register (Block Base=0x0800, Register Offset=0x04) . . . . . . . . . . . . . . . .114
Table 79. SPI-4 Egress Status Register (Block Base=0x0800, Register Offset=0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Table 80. SPI-4 Egress Diagnostics Register (Block Base=0x0800, Register Offset=0x06) . . . . . . . . . . . . . . . . . . . . . . . . . .115
Table 81. SPI-4 Egress Automatic Alignment Control Register (Block Base=0x0800, Register Offset=0x07) . . . . . . . . . . . . .115
Table 82. SPI-4 Egress Calendar Switch Control Register (Block Base = 0x0800, Register Offset=0x08) . . . . . . . . . . . . . . .116
Table 83. SPI-4 Egress Fill Level Register (Block Base=0x0800, Register Offset = 0x0B and 0x0C) . . . . . . . . . . . . . . . . . . .116
Table 84. SPI-4 Egress Max Fill Level Register (Block Base =0x0800, Register Offset = 0x0D and 0x0E) . . . . . . . . . . . . . .116
Table 85. SPI-4 Histogram Measure Launch Register (Block Base=0x0900 Register Offset=0x00) . . . . . . . . . . . . . . . . . . . .117
Table 86. SPI-4 Histogram Measure Status Register (Block Base=0x0900 Register Offset=0x01) . . . . . . . . . . . . . . . . . . . . .117
Table 87. SPI-4 Histogram Counter Register (Block Base=0x0900 Register Offset=0x02-0x0B) . . . . . . . . . . . . . . . . . . . . . .117
Table 88. SPI-4 Bit Alignment Result Register (Block Base=0x0900 Register Offset=0x0C-0x1E) . . . . . . . . . . . . . . . . . . . . .118
Table 89. SPI-4 Egress Data Lane Timing Control (Block Base=0x0900, Register Offset=0x2A) . . . . . . . . . . . . . . . . . . . . . .118
Table 90. SPI-4 Egress Data Control Lane Timing Control (Block Base=0x0900, Register Offset=0x2B) . . . . . . . . . . . . . . . .118
Table 91. SPI-4 Egress Data Clock Timing Control (BlockBase=0x0900, Register Offset=0x2C) . . . . . . . . . . . . . . . . . . . . . .119
Table 92. SPI-4 Egress Status Timing Control (Block Base=0x0900, Register Offset=0x2D) . . . . . . . . . . . . . . . . . . . . . . . . .119
Table 93. SPI-4 Egress Status Clock Timing Control (Block Base=0x0900, Register Offset=0x2E) . . . . . . . . . . . . . . . . . . . .120
Table 94. PFP Buffer Segment Assign Table (Block Base=0x01000/0x1800, Register Offset=0x00-0x3F) . . . . . . . . . . . . . .120
Table 95. PFP Packet Length Thresholds (Block Base=0x1100/0x1900, Register Offset=0x00-03F) . . . . . . . . . . . . . . . . . . .121
Table 96. PFP Queue Diagnose Table (Block Base=0x1200/0x1A00, Register Offset=0x00-0x3F) . . . . . . . . . . . . . . . . . . . .121
Table 97. PFP Packet Diagnose Table (Block Base=0x1300/0x1B00, Register Offset=0x00-03F) . . . . . . . . . . . . . . . . . . . . .121
Table 98. PFP Egress Burst Size Table (Block Base=0x1400/0x1C00, Register Offset=0x00-0x3F) . . . . . . . . . . . . . . . . . . .122
Table 99. PFP Egress Weight And Direction Register (Block Base=0x1500/0x1D00, Register Offset=0x00-03F) . . . . . . . . .122
Table 100. PFP Egress Packet Mode Control Register (Block Base=0x1600/0x1E00, Register Offset=0x00-0x3F) . . . . . . . . .123
Table 101. PFP Link Number Configuration Register (Block Base=0x1700/0x1F00, Register Offset=0x00) . . . . . . . . . . . . . . .123
Table 102. PFP Buffer Management Configuration Register (Block Base=0x1700/0x1F00, Register Offset=0x01) . . . . . . . . .123
Table 103. PFP Queue Weighting Enable Register (Block Base=0x1700/0x1F00, Register Offset=0x02) . . . . . . . . . . . . . . . .124
Table 104. PFP Flow Control Register (Block Base=0x1700/0x1F00, Register Offset=0x03) . . . . . . . . . . . . . . . . . . . . . . . . . .125
Table 105. PFP Test Register (Block Base=0x1700/0x1F00, Register Offset=0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Table 106. PFP Ingress Status Monitor Register - 1 (Block Base=0x1700/0x1F00, Register Offset=0x05) . . . . . . . . . . . . . . . .126
Table 107. PFP Ingress Status Monitor Register - 2 (Block Base=0x1700/0x1F00, Register Offset=0x06) . . . . . . . . . . . . . . . .126
IDT IDT88K8483
SPI-4 Ingress Configuration Register (Block Base=0x0300, Register Offset=0x01) . . . . . . . . . . . . . . . . . . . . . . . .106
Ingress Calendar Switch Register: Bit CAL_SEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
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October 20, 2006