IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 59

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

Generic Interface
Overview
configured by the MEM field in the
is enabled. The auxiliary interface outputs (except for the clock) can be powered down by setting to 1 the AUX_PDN field in the
Enable Register (p.
and 4 bits egress control bus. The 4 bits control bus carries the control information that indicates the transfer type, and the 32 bits data bus curries the
transfer data. The interface has also differential CLK ingress clock and differential CLK egress clock.
channel. The flow control mechanism provides both per link level flow control and interface level flow control.
shown in
Transfer Format for Normal Data
Figure 29
carries the LID information. LID[5:0] is mapped into B[5:0] of the first byte. The control field of the first transfer is SOP or SOT.
IDT IDT88K8483
The auxiliary interface has two modes: QDR-II interface mode and generic interface mode. The auxiliary interface mode (QDR-II or generic) is
The generic interface can be connected to an FPGA. The interface has 32 bits ingress data bus, 4 bits ingress control bus, 32 bits egress data bus
The ingress flow control messages are transmitted on the egress channel. The egress flow control messages are transmitted on the ingress
The G_VREF signal should be connected to 0.75V generated from the VDDH15 power supply using regulator or pot-divider like MAX1510 as
The generic interface format is defined to map 1-256 bytes payload in a proprietary transfer format. The transfer format for normal data is shown in
Figure 42 IDT88K8483 VDDA25 Filter Circuit
(DM is DUMMY information). The minimum payload transfer length is 2 words (1 word is 1 data cycle). The first word of a transfer
129). The interface is enabled by setting to 1 the AUX_EN field in the
CTL[3]
IDT88K8483
Auxiliary Interface Configuration Register (p.
G_EDAT[31:0]
G_IDAT[31:0]
G_ECTL[3:0]
G_ICTL[3:0]
G_ICLKN
G_ECLKN
Ctrl[1]
G_ECLKP
Ctrl[0]
Ctrl[1]
Ctrl[0]
G_ICLKP
G_VREF
G_IMP
CTL[0]
Figure 29 Generic Interface - Transfer Format for Normal Data
V
Figure 28 IDT88K8483 and FPGA connections
DDH15
100 OHM
B3/Dummy B2/DM
/2
DAT[31]
B7/DM
DM
DM
p.75.
59 of 162
B6/DM
DM
DM
129). The auxiliary interface has to be configured before the interface
B5/DM
B0/DM
DM
DM
EDAT[31:0]]
ECLKN
ICLKP
ECTL[3:0]
IDAT[31:0]
ICTL[3:0]
ECLKP
ICLKN
Auxiliary Interface Enable Register (p.
FPGA
D4/DM
DAT[0]
LID
DM
B0
October 20, 2006
129).
Auxiliary Interface