IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 140
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IDT88K8483
Manufacturer Part Number
IDT88K8483
Description
Spi-4 Exchange Document Issue 1.0
Manufacturer
Integrated Device Technology
Datasheet
1.IDT88K8483.pdf
(162 pages)
- Current page: 140 of 162
- Download datasheet (3Mb)
PMON Buffer T-M Overflow Indication Register
T_DIP4_EN
T_BUSERR_EN
T_ISYNC_EN
T_ESYNC_EN
M_DIP2_EN
M_DIP4_EN
M_BUSERR_EN
M_ISYNC_EN
M_ESYNC_EN
Note: Writing a 1 to any field in this register, causes an interrupt to be generated based on the occurrence of that particular event indicated in the corresponding
field in
OVFERFLOW[31:0]
IDT IDT88K8483
There are 2 registers.
Table
Field
Field
139. The interrupt appears as an active low on the INTB pin in the microprocessor interface.
Table 141 PMON Buffer T-M Overflow Indication Register (Block Base=0x0F00, Register Offset=0x02-0x03)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read /
Table 140 PMON Event Interrupt Enable Register (Block Base=0x0F00, Register Offset=0x01)
Read /
Write
Write
1:7
2:1
2:2
0:0-3:7
2:0
2:3
2:4
2:5
2:6
2:7
Bits
Bits
1
1
1
1
1
1
1
1
1
32
Length
Length
0
0
0
0
0
0
0
0
0
0
Reset
Reset
State
State
140 of 162
Tributary SPI4 DIP-4.
0: Disables the interrupt.
1: Enables the interrupt.
Tributary SPI4 bus error.
0: Disables the interrupt.
1: Enables the interrupt.
Tributary ingress synch status change.
0: Disables the interrupt.
1: Enables the interrupt.
Tributary Egress synch status change.
0: Disables the interrupt.
1: Enables the interrupt.
Main SPI4 DIP-2.
0: Disables the interrupt.
1: Enables the interrupt.
Main SPI4 DIP-4.
0: Disables the interrupt.
1: Enables the interrupt.
Main SPI4 bus error.
0: Disables the interrupt.
1: Enables the interrupt.
Main ingress synch status change.
0: Disables the interrupt.
1: Enables the interrupt.
Main Egress synch status change.
0: Disables the interrupt.
1: Enables the interrupt.
This register indicates the overflow on a per LID basis from the tributary to main
SPI-4 interface. Bit 0 of register with offset 0x02 indicates overflow for LID 0, bit 3
for LID 3, bit 0 of 2nd register with offset 0x03 indicates overflow for LID 32 and so
on.
Read 1: Indicates overflow for that LID.
Read 0: Indicates no overflow for that LID.
Write 1: Clears the bit.
Description
Description
October 20, 2006
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