IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 118

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

SPI-4 Egress Data Lane Timing Register
SPI-4 Egress Data Control Lane Timing Register
SPI-4 Bit Alignment Result Register
TAP[7:0]
Note: Please refer to SPI-4 Ingress Block Diagram (p. 43) and SPI-4 Egress State Block Diagram (p. 46) for bit alignment overview.
DTC0[1:0]
DTC1[1:0]
.
DTC15[1:0]
IDT IDT88K8483
CTLTC[1:0]
Field
Field
Field
Table 90
Table 89
R/W
R/W
R/W
R/W
R/W
Table 88 SPI-4 Bit Alignment Result Register (Block Base=0x0900 Register Offset=0x0C-0x1E)
SPI-4 Egress Data Control Lane Timing Control (Block Base=0x0900, Register Offset=0x2B)
R/W
Read /
Read /
Read /
Write
Write
Write
SPI-4 Egress Data Lane Timing Control (Block Base=0x0900, Register Offset=0x2A)
0:0-0:1
0:2-0:3
0:0-0:7
3:6-3:7
0:0-0:1
Bits
Bits
Bits
8
2
2
2
2
Length
Length
Length
2
0
0
0
0
0
0
Reset
Reset
Reset
State
State
State
118 of 162
TAP[3:0] covers the range of taps from 0 to 8. TAP[7:4] covers the range of taps
from 5 to 14. The value selected from the counter register field C[n] Table 87, is writ-
ten into the TAP field. This is used to select the received bit stream from the 10
samples after the HISTOGRAM measure is launched.There are 19 registers in total.
This register is used to manually align the phase of data lane n by adding between
0.1 and 0.3 clock cycles of delay.
DTCn [1:0] is used for adding 0.1 clock cycle units of output delay to the SPI-
4 egress data lane n.
DTCn[1:0]=0=No added delay.
DTCn[1:0]=1=Add 0.1 clock cycle of delay to data lane n.
DTCn[1:0]=2=Add 0.2 clock cycles of delay to data lane n.
DTCn[1:0]=3=Add 0.3 clock cycles of delay to data lane n.
This register is used to manually align the phase of the control lane by adding
between 0.1 clock cycle and 0.3 clock cycles of delay.
CTLTC [1:0] Used for adding 0.1 clock cycle units of output delay to the
SPI-4 egress control output.
CTLTC
CTLTC
CTLTC
CTLTC
[1:0]=0=No added delay.
[1:0]=1=Add 0.1 clock cycle of delay to the control output.
[1:0]=2=Add 0.2 clock cycles of delay to the control output.
[1:0]=3=Add 0.3 clock cycles of delay to the control output.
Description
Description
Description
October 20, 2006