IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 62

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

Microprocessor Interface
Overview
mode, and when SPIEN signal is set to 1, the interface is in serial mode.
Interface - Parallel Mode
rupt signals. In addition there is a mode signal: MPM. When MPM signal is set to 1, the interface is in Intel mode, and when MPM signal is cleared to
0, the interface is in Motorola mode.
signals.The microprocessor interface timing is based on the main clock domain. One microprocessor interface cycle is four main clock cycles.
Embedded Processor Download
from the host to the embedded processor. Refer to
further downloading steps take place as indicated in the flowchart below.
bit words, the lower byte should be swapped with the upper byte.
IDT IDT88K8483
The microprocessor interface can be in serial mode or in parallel mode. When the external signal SPIEN is cleared to 0, the interface is in parallel
The parallel microprocessor interface can be connected directly to a suitable processor or to a FPGA as shown in
.
The serial microprocessor interface can be connected directly to a suitable processor or to a FPGA. The interface has data, chip select and clock
The embedded processor has 2 mailboxes, I_FIFO and O_FIFO each of which has a 32 byte FIFO. Mailbox I_FIFO is used for firmware download
The download should take place in the little endian format. If the download file is in big endian format and since the downloading takes place in 16
The embedded processor is first checked to see if it is ready for download. This is done by reading direct register 0x16. If the result is 0x1, then
p.62. The interface has 8 bits data bus and 6 bits address bus. The interface has also write, read, chip select and inter-
IDT88K8483
ADR[5:0]
DAT[7:0]
SPIEN
WRB
MPM
INTB
RDB
CSB
Figure 31 Microprocessor Interface - Parallel Mode
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and
VDD
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for registers related to the mailbox FIFOs.
INTB
DAT[7:0]
WRB
ADD[5:0]
RDB
CSB
Processor / FPGA
Figure 31 Microprocessor
October 20, 2006