IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 47

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

Egress associated status channel
Bit alignment
Each consecutive pairs of sampled values are XORed and accumulated during a fixed observation window to generate transition edge histogram.
process is indicated by a BUSY flag in the
launched. The BUSY field is auto cleared to 0 when the measurement is finished. The status channel TAP is configured by the AUTO_ALIGN field in
the
Register (p. 117)
De-skew
then the E_DSK_OOR field in the
Status Termination
number of consecutive DIP-2 error-free values cause a transition from OUT_OF_SYNCH to IN_SYNCH state. This number is configured by
Egress Configuration Register (p.
configured in the
OUT_OF_SYNCH state. In LVTTL protocol mode, 12 consecutive ‘11’ will force the machine to OUT_OF_SYNCH state. The machine’s state is indi-
cated by E_SYNCV field in the
enabled.
then two sets of calendars mode are used. In this case, a calendar selection word must be placed following the framing bit.
tion word is fixed to 01b. If CAL_SEL field is set to 1, then the device selects calendar 1, and the selection word is fixed to 10b.
IDT IDT88K8483
The alignment selection is programed by AUTO_ALIGN flag in the
The device is responsible for edge transition histogram for each lane. The data is sampled by 10-phased shifted clock during each clock cycle.
The measure histogram is triggered by writing to the LANE field in the
The bit alignment sequence is as follows:
- Write lane number in the LANE field in the
- Poll the BUSY field in the
- Write the selected Tap value to TAP field in the
The De-skew block can de-skew +/-1bit. For diagnostic purpose, an out of range offset between lines is provided. If deskew is more than 2 bits,
The protocol (LVDS/LVTTL) is configured by SPI4_LVDSSTA input pin. The status channel has 2 states, IN_SYNCH and OUT_OF_SYNCH. A
The device supports one or two sets of calendars. If E_CSW_EN field in the
If CAL_SEL field in the
SPI-4 Egress Automatic Alignment Control Register (p.
which indicates the counter value. The counter value is used to select the tap.
SPI-4 Egress Configuration Register (p.
SPI-4 Egress Calendar Switch Control Register (p. 116)
A=a number consecutive DIP-2 error free
B=a number of consecutive DIP-2 error,training, port disabled or
reset
SPI-4 Histogram Measure Status Register (p.
SPI-4 Egress Status Register (p.
SPI-4 Egress Status Register (p. 115)
113). A number of consecutive DIP-2 errors will force the machine to OUT_OF_SYNCH state. This number is
Out of
synch
SPI-4 Histogram Measure Status Register (p.
SPI-4 Histogram Measure Launch Register (p.
SPI-4 Bit Alignment Result Register (p.
Figure 19 Status Channel State Machine
A
B
115).
113). In LVDS protocol mode, 12 consecutive “11” will force the machine to
115). Any transition on the E_SYNCV field is captured, and generates an interrupt if
IN_SYNCH
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SPI-4 Egress Automatic Alignment Control Register (p.
is set. E_DSK_OOR field is cleared when in range.
117). If BUSY is 0, then read the C[n] field in the
SPI-4 Histogram Measure Launch Register (p.
SPI-4 Egress Calendar Switch Control Register (p. 116)
is cleared to 0, then the device selects calendar 0, and the selec-
117). The BUSY field is set to 1 when a measurement is
118).
117).
SPI-4 Histogram Counter
117). The measurement
115).
October 20, 2006
is set to 1,
SPI-4