IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 72

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

ration. This allows the internal logic to be stable. During T2 (at least 1ms delay) the device performs internal memories initialization, and during T3 (at
least 1ms delay) the device run a boot code from the internal embedded processor ROM.
CHIP_READY field is 1, the user should download the firmware binary file from the external microprocessor to the IDT88K8483 embedded processor
RAM.
JTAG
testing costs by eliminating the need for a sophisticated in-circuit test equipment. The inclusion of boundary-scan registers in integrated circuits greatly
improves the testability of boards. Boundary scan provides a mechanism for testing component input, output and inter-connections. Devices
containing boundary scan have the capability of driving or observing the logic levels on I/O pins by utilizing the TAP (Test Access Port). The TAP
controller, a 16-state Moore-type state machine, dictates the control of all JTAG activities through four pins: TDI (Test Data Input), TDO (Test Data
Output), TMS (Test Mode Select), and TCK (Test Clock).
test controller and returns there, through the scan path, to TDO. To test the external interconnect, devices drive values at their outputs and observe
input values received from other devices. An external test controller compares the received data with expected results. Any device can be temporarily
removed from the boundary-scan path by bypassing its internal shift registers, and passing the serial data directly onto the next device. This allows
efficient testing of a selected device without incurring the overhead of traversing through other devices. JTAG testing can also be used to check the
inter connectivity of external memory devices by generating read and write test vectors independent of the chip functionality. The read and write vector
results can then be read back to ensure that the memory devices are connected correctly.
Design for Test
ular ball grid arrays require confidence in the correct assembly of the initial prototype boards. The IDT88K8483 chip has 672 pins FCBGA. Bed-of-
nails testing does not allow the testing of BGA mounting to the board. JTAG testing is very effective at isolating assembly errors down to individual
signals in a very short time.
ularly BGAs not mounted correctly to the board. Using JTAG enables the issues to be immediately identified if design for test is considered from the
outset. It is possible for the customer to generate comprehensive JTAG tests within a week of becoming familiar with the appropriate equipment and
tools. The time between Gerber files going to fabrication and the board’s return can be used to generate the appropriate JTAG tests, thus limiting
schedule impact. The effort is also much less than that required to develop functional diagnostic tests to exercise and test every individual pin. JTAG
results in considerable time saving during the prototype bring-up, which can be one of the most significant causes of delays in overall time-to-market.
assembly before attempting to run any functional tests.
IDT88K8483 JTAG Testing
Input), TDO (Test Data Output), TMS (Test Mode Select), TCK (Test Clock), and TRSTB (Test Reset). The TCK clock frequency is up to 10MHz.
Chain
device. Also, the TCK, TMS and TRSTB signals of all the devices should be connected together and driven from the JTAG connector.
IDT IDT88K8483
After the RESETB pulse ends, a delay of 2ms should be added (symbols “T2” and “T3”) before accessing the device for initialization and configu-
After T3, the user should poll the CHIP_READY field in the
IEEE Boundary Scan standard 1149.1, informally known as JTAG (Joint Test Action Group), is a testing standard that uses software to reduce
Data is passed serially from one device to the next, thus forming a boundary-scan path or chain from TDI (Test Data Input) that originates at the
IDT strongly recommends that its customers use JTAG testing for both prototypes and production boards. Large pin count devices, and in partic-
During the board bring-up process, several weeks have been spent identifying problems that turned out to be incorrectly assembled boards, partic-
IDT's bring-up strategy is based on the assumption that the customer’s board is correctly assembled, and has been tested to ensure proper
The IDT88K8483 supports board-level testing through the use of a JTAG test port. The test port comprises the following pins: JTDI (Test Data
When JTAG testing is used on the board, all the devices should be JTAG daisy-chained, TDO to TDI as shown in
p.73. Note that the pins on the JTAG connector are named so that TDI drives the TDI of the first device and TDO is driven by TDO of the last
Embedded Processor State Register (p.
72 of 162
92), and wait until it is 1. When the
Figure 39 JTAG Daisy
October 20, 2006