IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 39

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

External Interfaces
FPGA or a QDR-II bus, a pin-selectable serial or parallel microprocessor interface, a JTAG interface, and five general purpose input or output (GPIO)
pins. The following information contains a set of the highlights of the features supported from the relevant standards, and a description of additional
features implemented to enhance the usability of these interfaces for the system architect.
SPI-4A AND SPI-4B
SPI-4M
FPGA INTERFACE
QDR-II INTERFACE
MICROPROCESSOR INTERFACE
IDT IDT88K8483
Refer to the OIF SPI-4 implementation agreement (OIF-SPI-4-02.1) for full details.
The FPGA interface is shared with the QDR-II interface. Selecting the FPGA interface enables the following features:
The QDR-II interface is shared with the FPGA interface. Selecting the QDR-II interface enables the following features:
Parallel microprocessor interface:
Refer to the OIF SPI-4 implementation agreement (OIF-SPI-4-02.1) for full details.
The external interfaces provided on the IDT88K8483 device are three SPI-4 interfaces, SPI-4A, SPI-4B and SPI-4M, an interface to either a
– Two instantiations of the SPI-4 interface
– Clock rate is
– Link and PHY interfaces are supported
– Logical port address range of 0 – 255 with support for between 1 and 64 simultaneously active logical ports
– MAXBURST parameters configurable from 16 to 256 bytes in 16 byte multiples
– 256-entry FIFO status calendar
– Quarter-clock-rate LVTTL, or full-rate LVDS FIFO status signals are selectable per SPI-4 port
– One instantiation of the SPI-4 Main interface
– Clock rate is 87 - 450 MHz DDR
– Link and PHY interfaces are supported
– Logical port address range of 0 – 255 with support for between 1 and 128 simultaneously active logical ports
– MAXBURST parameters configurable from 16 to 256 bytes in 16 byte multiples
– 256-entry FIFO status calendar
– Quarter-clock-rate LVTTL, or full-rate LVDS FIFO status signals are selectable per SPI-4 port
– Clock rate is 160 - 200 MHz DDR source-synchronous
– Logical port address range of 0 – 63 with support for 64 simultaneously active logical ports
– DDR HSTL logic levels
– Clock rate is 160 - 200 MHz QDR-II
– Up to 18 Mbit of QDR-II memory is supported
– QDR-II HSTL logic levels
– Eight bit data bus
– Six bit address bus
– Pin-selectable Intel or Motorola control signals
– Direct accessed space used for quick interrupt processing
– Expanded indirect access space used for provisioning
– Read operations to a reserved address or reserved bit fields return 0
– Write operations to reserved addresses or bit fields are ignored
77.76
- 450 MHz DDR
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October 20, 2006