IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 119

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

SPI-4 Egress Data Clock Timing Register
SPI-4 Egress Status Timing Register
IDT IDT88K8483
DCTC[0:3]
STC0[0:1]
STC1[0:1]
Field
Field
R/W
R/W
R/W
Read /
Read /
Table 91 SPI-4 Egress Data Clock Timing Control (BlockBase=0x0900, Register Offset=0x2C)
Write
Write
Table 92 SPI-4 Egress Status Timing Control (Block Base=0x0900, Register Offset=0x2D)
0:0-0:3
0:0-0:1
0:2-0:3
Bits
Bits
Length
Length
4
2
2
0
0
0
Reset
Reset
State
State
119 of 162
This register is used to manually align the phase of the SPI-4 egress data clock to
the data and control lanes by adding from 0.1 clock cycle to 0.9 clock cycles of
delay to the data clock output. Note that the clock delay value is not monotonically
related to the value encoded in the bit field [3:0].
DCTC [3:0] Used for adding 0.1 clock cycle units of output delay to the
SPI-4 egress data clock.
[3:0]=0=No added delay
[3:0]=1=Add 0.1 clock cycle of delay to the SPI-4 egress data clock.
[3:0]=3=Add 0.2 clock cycles of delay to the SPI-4 egress data clock.
[3:0]=2=Add 0.3 clock cycles of delay to the SPI-4 egress data clock.
[3:0]=7=Add 0.4 clock cycles of delay to the SPI-4 egress data clock.
[3:0]=6=Add 0.5 clock cycles of delay to the SPI-4 egress data clock.
[3:0]=4=Add 0.6 clock cycles of delay to the SPI-4 egress data clock.
[3:0]=5=Add 0.7 clock cycles of delay to the SPI-4 egress data clock.
[3:0]=F=Add 0.8 clock cycles of delay to the SPI-4 egress data clock.
[3:0]=E=Add 0.9 clock cycles of delay to the SPI-4 egress data clock.
This register is used to manually align the phase of the status lane n by adding from
0.1 clock cycle to 0.3 clock cycles of delay. The STC0[1:0] and STC0[1:0] fields are
valid only for LVDS status and are not used for LVTTL status.
STCn [1:0] Used for adding 0.1 clock cycle units of output delay to SPI-
4 egress status lane n.
[1:0]=0=No added delay.
[1:0]=1=Add 0.1 clock cycle of delay to status lane n.
[1:0]=2=Add 0.2 clock cycles of delay to status lane n.
[1:0]=3=Add 0.3 clock cycles of delay to status lane n.
Description
Description
October 20, 2006